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Fri, 26 Feb 2021 01:58:09 -0500 (EST) From: Andrew Jeffery To: qemu-arm@nongnu.org Subject: [PATCH 0/4] aspeed: LPC peripheral controller devices Date: Fri, 26 Feb 2021 17:27:54 +1030 Message-Id: <20210226065758.547824-1-andrew@aj.id.au> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Received-SPF: pass client-ip=66.111.4.25; envelope-from=andrew@aj.id.au; helo=out1-smtp.messagingengine.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, ryan_chen@aspeedtech.com, minyard@acm.org, qemu-devel@nongnu.org, clg@kaod.org, joel@jms.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hello, This series adds support for some of the LPC[1] peripherals found in Aspeed BMC SoCs. BMCs typically provide a number of features to their host via LPC that include but are not limited to: 1. Mapping LPC firmware cycles to BMC-controlled flash devices 2. UART(s) for system console routing 3. POST code routing 4. Keyboard-Controller-Style (KCS) IPMI devices 5. Block Transfer (BT) IPMI devices 6. A SuperIO controller for management of LPC devices and miscellaneous functionality [1] https://www.intel.com/content/dam/www/program/design/us/en/documents/low-pin-count-interface-specification.pdf Specifically, this series adds basic support for functions 1 and 4 above, handling the BMC firmware configuring the bridge mapping LPC firmware cycles onto its AHB as well as support for four KCS devices. Aspeed's LPC controller is not a straight-forward device by any stretch. It contains at least the capabilities outlined above, in the sense that it's not possible to cleanly separate the different functions into distinct MMIO sub-regions: Registers for the various bits of functionality have the feel of arbitrary placement with a nod to feature-creep and backwards compatibility. Further, the conceptually coherent pieces of functionality often come with the ability to issue interrupts, though for the AST2400 and AST2500 there is one shared VIC IRQ for all LPC "subdevices". By contrast the AST2600 gives each subdevice a distinct IRQ via the GIC. All this combined leads to some complexity regarding the interrupts and handling the MMIO accesses (in terms of mapping the access back to the function it's affecting). Finally, as a point of clarity, Aspeed BMCs also contain an LPC Host Controller to master the LPC bus. This series does not concern itself with the LPC Host Controller function, only with a subset of the peripheral devices the BMC presents to the host. I've tested the series using a combination of the ast2600-evb, witherspoon-bmc and romulus-bmc machines along with a set of recently-posted patches for Linux[2]. Please review! Andrew [2] https://lore.kernel.org/openbmc/20210219142523.3464540-1-andrew@aj.id.au/T/#m1e2029e7aa2be3056320e8d46b3b5b1539a776b4 Andrew Jeffery (3): arm: ast2600: Force a multiple of 32 of IRQs for the GIC arm: ast2600: Fix iBT IRQ ID hw/misc: Model KCS devices in the Aspeed LPC controller Cédric Le Goater (1): hw/misc: Add a basic Aspeed LPC controller model docs/system/arm/aspeed.rst | 2 +- hw/arm/aspeed_ast2600.c | 44 +++- hw/arm/aspeed_soc.c | 34 ++- hw/misc/aspeed_lpc.c | 485 +++++++++++++++++++++++++++++++++++ hw/misc/meson.build | 7 +- include/hw/arm/aspeed_soc.h | 3 + include/hw/misc/aspeed_lpc.h | 47 ++++ 7 files changed, 615 insertions(+), 7 deletions(-) create mode 100644 hw/misc/aspeed_lpc.c create mode 100644 include/hw/misc/aspeed_lpc.h base-commit: 51db2d7cf26d05a961ec0ee0eb773594b32cc4a1