[v4,0/3] target/arm: Add support for FEAT_TLBIOS and FEAT_TLBIRANGE

Message

Rebecca Cran March 16, 2021, 3:49 p.m. UTC

ARMv8.4 adds the mandatory FEAT_TLBIOS and FEAT_TLBIRANGE. 
They provides TLBI maintenance instructions that extend to the Outer
Shareable domain and that apply to a range of input addresses.

Changes from v3 to v4:

o Adapted code from the existing flush_page_bits_* functions to support
  flushing a range of addresses.
o Changed the API from num_pages to length.
o Removed the exception generation from tlbi_aa64_range_get_num_pages.
o The addr is no longer passed into tlbi_aa64_range_get_num_pages.
o Other changes based on feedback.

Rebecca Cran (3):
  target/arm: Add support for FEAT_TLBIRANGE
  target/arm: Add support for FEAT_TLBIOS
  target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type

 accel/tcg/cputlb.c      | 135 +++++++
 include/exec/exec-all.h |  45 +++
 target/arm/cpu.h        |  10 +
 target/arm/cpu64.c      |   1 +
 target/arm/helper.c     | 393 ++++++++++++++++++++
 5 files changed, 584 insertions(+)

Comments

[e-mail] March 16, 2021, 5:03 p.m. UTC | #1

Patchew URL: https://patchew.org/QEMU/[e-mail]/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: [e-mail]
Subject: [PATCH v4 0/3] target/arm: Add support for FEAT_TLBIOS and FEAT_TLBIRANGE

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 - [tag update]      patchew/[e-mail] -> patchew/[e-mail]
 - [tag update]      patchew/[e-mail] -> patchew/[e-mail]
 - [tag update]      patchew/[e-mail] -> patchew/[e-mail]
 - [tag update]      patchew/[e-mail] -> patchew/[e-mail]
 * [new tag]         patchew/[e-mail] -> patchew/[e-mail]
Switched to a new branch 'test'
e9f3e00 target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type
8bcac4c target/arm: Add support for FEAT_TLBIOS
f171966 target/arm: Add support for FEAT_TLBIRANGE

=== OUTPUT BEGIN ===
1/3 Checking commit f17196657ee3 (target/arm: Add support for FEAT_TLBIRANGE)
WARNING: line over 80 characters
#218: FILE: include/exec/exec-all.h:354:
+static inline void tlb_flush_page_range_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu,

WARNING: line over 80 characters
#219: FILE: include/exec/exec-all.h:355:
+                                                                       target_ulong addr,

ERROR: line over 90 characters
#220: FILE: include/exec/exec-all.h:356:
+                                                                       target_ulong length,

WARNING: line over 80 characters
#221: FILE: include/exec/exec-all.h:357:
+                                                                       uint16_t idxmap,

WARNING: line over 80 characters
#222: FILE: include/exec/exec-all.h:358:
+                                                                       unsigned bits)

total: 1 errors, 4 warnings, 545 lines checked

Patch 1/3 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

2/3 Checking commit 8bcac4c04c8e (target/arm: Add support for FEAT_TLBIOS)
3/3 Checking commit e9f3e002d73d (target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/[e-mail]/testing.checkpatch/?type=message.
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