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Fri, 16 Apr 2021 12:00:00 -0700 (PDT) Received: from localhost.localdomain ([71.212.131.83]) by smtp.gmail.com with ESMTPSA id d7sm1988337pfv.197.2021.04.16.11.59.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 16 Apr 2021 12:00:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 for-6.1 00/39] target/arm: enforce alignment Date: Fri, 16 Apr 2021 11:59:29 -0700 Message-Id: <20210416185959.1520974-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Based-on: 20210416183106.1516563-1-richard.henderson@linaro.org ("[PATCH v5 for-6.1 0/9] target/arm mte fixes") Patches lacking review: 02-target-arm-Rename-TBFLAG_A32-SCTLR_B.patch 03-target-arm-Rename-TBFLAG_ANY-PSTATE_SS.patch 04-target-arm-Add-wrapper-macros-for-accessing-tbfla.patch 05-target-arm-Introduce-CPUARMTBFlags.patch 06-target-arm-Move-mode-specific-TB-flags-to-tb-cs_b.patch 07-target-arm-Move-TBFLAG_AM32-bits-to-the-top.patch 08-target-arm-Move-TBFLAG_ANY-bits-to-the-bottom.patch 09-target-arm-Add-ALIGN_MEM-to-TBFLAG_ANY.patch 21-target-arm-Enforce-alignment-for-VLDn-all-lanes.patch Changes for v4: * Rebase on mte fixes and fixup minor conflict. Changes for v3: * Move TBFLAG_{A64,A32,M32,AM32} to tb->cs_base, leaving only TBFLAG_ANY in tb->flags. This solves our current problem of running out of bits in tb->flags. * Dropped "Enforce alignment for sve unpredicated LDR/STR"; there are more changes required for SVE. Changes for v2: * Rearranged things a bit, which has made it easy to support SCTLR.A/CCR.UNALIGN_TRAP. At least for non-sve code, where we issue tcg load/store operations. Predicated sve load/stores will require more work within the helpers. r~ Richard Henderson (30): target/arm: Fix decode of align in VLDST_single target/arm: Rename TBFLAG_A32, SCTLR_B target/arm: Rename TBFLAG_ANY, PSTATE_SS target/arm: Add wrapper macros for accessing tbflags target/arm: Introduce CPUARMTBFlags target/arm: Move mode specific TB flags to tb->cs_base target/arm: Move TBFLAG_AM32 bits to the top target/arm: Move TBFLAG_ANY bits to the bottom target/arm: Add ALIGN_MEM to TBFLAG_ANY target/arm: Adjust gen_aa32_{ld,st}_i32 for align+endianness target/arm: Merge gen_aa32_frob64 into gen_aa32_ld_i64 target/arm: Fix SCTLR_B test for TCGv_i64 load/store target/arm: Adjust gen_aa32_{ld,st}_i64 for align+endianness target/arm: Enforce word alignment for LDRD/STRD target/arm: Enforce alignment for LDA/LDAH/STL/STLH target/arm: Enforce alignment for LDM/STM target/arm: Enforce alignment for RFE target/arm: Enforce alignment for SRS target/arm: Enforce alignment for VLDM/VSTM target/arm: Enforce alignment for VLDR/VSTR target/arm: Enforce alignment for VLDn (all lanes) target/arm: Enforce alignment for VLDn/VSTn (multiple) target/arm: Enforce alignment for VLDn/VSTn (single) target/arm: Use finalize_memop for aa64 gpr load/store target/arm: Use finalize_memop for aa64 fpr load/store target/arm: Enforce alignment for aa64 load-acq/store-rel target/arm: Use MemOp for size + endian in aa64 vector ld/st target/arm: Enforce alignment for aa64 vector LDn/STn (multiple) target/arm: Enforce alignment for aa64 vector LDn/STn (single) target/arm: Enforce alignment for sve LD1R target/arm/cpu.h | 105 ++++++++----- target/arm/translate.h | 38 +++++ target/arm/neon-ls.decode | 4 +- target/arm/helper-a64.c | 2 +- target/arm/helper.c | 160 +++++++++++--------- target/arm/translate-a64.c | 214 +++++++++++++------------- target/arm/translate-sve.c | 2 +- target/arm/translate.c | 258 +++++++++++++++++--------------- target/arm/translate-neon.c.inc | 117 ++++++++++++--- target/arm/translate-vfp.c.inc | 20 +-- 10 files changed, 555 insertions(+), 365 deletions(-)