[v6,00/17] support subsets of bitmanip extension

Message

Frank Chang May 5, 2021, 4:06 p.m. UTC

From: Frank Chang <[e-mail]>

This patchset implements RISC-V B-extension v0.93 version Zba, Zbb and
Zbs subset instructions. Some Zbp instructions are also implemented as
they have similar behavior with their Zba-, Zbb- and Zbs-family
instructions or for Zbb pseudo instructions (e.g. rev8, orc.b).

Specification:
https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.93.pdf

The port is available here:
https://github.com/sifive/qemu/tree/rvb-upstream-v6

To test rvb implementation, specify cpu argument with 'x-b=true' or
'x-b=true,bext_spec=v0.93'to enable B-extension support.

Changelog:

v6:
 * rebase riscv-to-apply.next branch.
 * remove all #ifdef TARGET_RISCV64 macros.

v5:
 * add bext_spec cpu option, default set to v0.93.
 * rebase master branch.

v4:
 * Remove 'rd != 0' checks from immediate shift instructions.

v3:
 * Convert existing immediate shift instructions to use gen_shifti()
   and gen_shiftiw() interfaces.
 * Rename *u.w instructions to *.uw.
 * Rename sb* instructions to b*.
 * Rename pcnt* instructions to cpop*.

v2:
 * Add gen_shifti(), gen_shiftw(), gen_shiftiw() helper functions.
 * Remove addwu, subwu and addiwu instructions as they are not longer
   exist in latest draft.
 * Optimize implementation with cleaner tcg ops.

Frank Chang (6):
  target/riscv: rvb: count bits set
  target/riscv: add gen_shifti() and gen_shiftiw() helper functions
  target/riscv: rvb: single-bit instructions
  target/riscv: rvb: generalized reverse
  target/riscv: rvb: generalized or-combine
  target/riscv: rvb: add b-ext version cpu option

Kito Cheng (11):
  target/riscv: reformat @sh format encoding for B-extension
  target/riscv: rvb: count leading/trailing zeros
  target/riscv: rvb: logic-with-negate
  target/riscv: rvb: pack two words into one register
  target/riscv: rvb: min/max instructions
  target/riscv: rvb: sign-extend instructions
  target/riscv: rvb: shift ones
  target/riscv: rvb: rotate (left/right)
  target/riscv: rvb: address calculation
  target/riscv: rvb: add/shift with prefix zero-extend
  target/riscv: rvb: support and turn on B-extension from command line

 target/riscv/bitmanip_helper.c          |  90 +++++
 target/riscv/cpu.c                      |  27 ++
 target/riscv/cpu.h                      |   5 +
 target/riscv/helper.h                   |   6 +
 target/riscv/insn32.decode              |  87 ++++-
 target/riscv/insn_trans/trans_rvb.c.inc | 438 ++++++++++++++++++++++++
 target/riscv/insn_trans/trans_rvi.c.inc |  54 +--
 target/riscv/meson.build                |   1 +
 target/riscv/translate.c                | 306 +++++++++++++++++
 9 files changed, 958 insertions(+), 56 deletions(-)
 create mode 100644 target/riscv/bitmanip_helper.c
 create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc

--
2.17.1

Comments

Alistair Francis May 27, 2021, 10:08 p.m. UTC | #1

On Thu, May 6, 2021 at 2:11 AM <[e-mail]> wrote:
>
> From: Frank Chang <[e-mail]>
>
> This patchset implements RISC-V B-extension v0.93 version Zba, Zbb and
> Zbs subset instructions. Some Zbp instructions are also implemented as
> they have similar behavior with their Zba-, Zbb- and Zbs-family
> instructions or for Zbb pseudo instructions (e.g. rev8, orc.b).
>
> Specification:
> https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.93.pdf
>
> The port is available here:
> https://github.com/sifive/qemu/tree/rvb-upstream-v6
>
> To test rvb implementation, specify cpu argument with 'x-b=true' or
> 'x-b=true,bext_spec=v0.93'to enable B-extension support.
>
> Changelog:
>
> v6:
>  * rebase riscv-to-apply.next branch.
>  * remove all #ifdef TARGET_RISCV64 macros.
>
> v5:
>  * add bext_spec cpu option, default set to v0.93.
>  * rebase master branch.
>
> v4:
>  * Remove 'rd != 0' checks from immediate shift instructions.
>
> v3:
>  * Convert existing immediate shift instructions to use gen_shifti()
>    and gen_shiftiw() interfaces.
>  * Rename *u.w instructions to *.uw.
>  * Rename sb* instructions to b*.
>  * Rename pcnt* instructions to cpop*.
>
> v2:
>  * Add gen_shifti(), gen_shiftw(), gen_shiftiw() helper functions.
>  * Remove addwu, subwu and addiwu instructions as they are not longer
>    exist in latest draft.
>  * Optimize implementation with cleaner tcg ops.
>
> Frank Chang (6):
>   target/riscv: rvb: count bits set
>   target/riscv: add gen_shifti() and gen_shiftiw() helper functions
>   target/riscv: rvb: single-bit instructions
>   target/riscv: rvb: generalized reverse
>   target/riscv: rvb: generalized or-combine
>   target/riscv: rvb: add b-ext version cpu option
>
> Kito Cheng (11):
>   target/riscv: reformat @sh format encoding for B-extension
>   target/riscv: rvb: count leading/trailing zeros
>   target/riscv: rvb: logic-with-negate
>   target/riscv: rvb: pack two words into one register
>   target/riscv: rvb: min/max instructions
>   target/riscv: rvb: sign-extend instructions
>   target/riscv: rvb: shift ones
>   target/riscv: rvb: rotate (left/right)
>   target/riscv: rvb: address calculation
>   target/riscv: rvb: add/shift with prefix zero-extend
>   target/riscv: rvb: support and turn on B-extension from command line

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/bitmanip_helper.c          |  90 +++++
>  target/riscv/cpu.c                      |  27 ++
>  target/riscv/cpu.h                      |   5 +
>  target/riscv/helper.h                   |   6 +
>  target/riscv/insn32.decode              |  87 ++++-
>  target/riscv/insn_trans/trans_rvb.c.inc | 438 ++++++++++++++++++++++++
>  target/riscv/insn_trans/trans_rvi.c.inc |  54 +--
>  target/riscv/meson.build                |   1 +
>  target/riscv/translate.c                | 306 +++++++++++++++++
>  9 files changed, 958 insertions(+), 56 deletions(-)
>  create mode 100644 target/riscv/bitmanip_helper.c
>  create mode 100644 target/riscv/insn_trans/trans_rvb.c.inc
>
> --
> 2.17.1
>
>