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Fri, 14 May 2021 14:33:07 +0000 From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Subject: [PATCH 0/4] AIA local interrupt CSR support Date: Fri, 14 May 2021 20:02:38 +0530 Message-Id: <20210514143242.377645-1-anup.patel@wdc.com> X-Mailer: git-send-email 2.25.1 X-Originating-IP: [122.179.90.73] X-ClientProxiedBy: MAXPR0101CA0046.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:d::32) To CO6PR04MB7812.namprd04.prod.outlook.com (2603:10b6:303:138::6) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from wdc.com (122.179.90.73) by MAXPR0101CA0046.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:d::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4108.25 via Frontend Transport; Fri, 14 May 2021 14:33:03 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7bec1e6f-2167-42e2-322d-08d916e53076 X-MS-TrafficTypeDiagnostic: CO6PR04MB7810: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: WDCIPOUTBOUND: EOP-TRUE X-MS-Oob-TLC-OOBClassifiers: OLM:8273; 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envelope-from=prvs=761afde0a=Anup.Patel@wdc.com; helo=esa4.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, MSGID_FROM_MTA_HEADER=0.001, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The advanced interrupt architecture (AIA) extends the per-HART local interrupt support. Along with this, it also adds IMSIC (MSI contrllor) and Advanced PLIC (wired interrupt controller). The latest AIA draft specification can be found here: http://jhauser.us/private/RISCV-AIA/riscv-interrupts-021.pdf This series adds initial AIA support in QEMU which includes emulating all AIA local CSR. To enable AIA in QEMU, we just need to pass "x-aia=true" paramenter in "-cpu" QEMU command-line. To test series, we require OpenSBI and Linux with AIA support which can be found in riscv_aia_v1 branch at: https://github.com/avpatel/opensbi.git https://github.com/avpatel/linux.git Anup Patel (4): target/riscv: Add defines for AIA local interrupt CSRs target/riscv: Add CPU feature for AIA CSRs target/riscv: Implement AIA local interrupt CSRs hw/riscv: virt: Use AIA INTC compatible string when available hw/riscv/virt.c | 11 +- target/riscv/cpu.c | 32 +- target/riscv/cpu.h | 56 +- target/riscv/cpu_bits.h | 128 +++++ target/riscv/cpu_helper.c | 245 ++++++++- target/riscv/csr.c | 1059 +++++++++++++++++++++++++++++++++++-- target/riscv/machine.c | 26 +- 7 files changed, 1454 insertions(+), 103 deletions(-)