From patchwork Mon May 17 10:51:17 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 12261539 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2DC5BC433B4 for ; Mon, 17 May 2021 10:53:24 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BF83261074 for ; Mon, 17 May 2021 10:53:23 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BF83261074 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=amsat.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:53668 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1liasE-0006gT-Ov for qemu-devel@archiver.kernel.org; Mon, 17 May 2021 06:53:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55452) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1liaqi-0003nu-HF; Mon, 17 May 2021 06:51:48 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:45694) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1liaqg-0006FU-Eo; Mon, 17 May 2021 06:51:48 -0400 Received: by mail-wr1-x430.google.com with SMTP id h4so5850832wrt.12; Mon, 17 May 2021 03:51:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=4J6gCjiLvFV0qYFBY/UaRpAcHcZtCFan7YLoPArbzt0=; b=MLgm96ViwoMhrCHAotIusRn781Lh7mbyKi1yRHhJpNsGcSWVQbCBJw136f9y8s2NIS 75U7aWpQBrU6EShJpkydGYHqGeGs7NzMkihuXM8IiT5KLFZ5lYlmj4lJlx23m8cM4oD7 vxdTXGc9+rFhPMwZ0f8bIsJtPhW2B8f4ksNgmBG0Kk8LgRWf7lCa84piLlGOdC8At/2Y l7E1fJ4TwWgR+GuNDfKZcdO7wDxOAf0d9JF85zO7m51xYeyPw1gxiQ+Y0yk6B/t3jYWJ cuwwu4Um409hvCOsyOiaAgHcLO/yenD7a27KkselbcV6BUu0nV4kCaoAPGPNB+FygwTc sTMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=4J6gCjiLvFV0qYFBY/UaRpAcHcZtCFan7YLoPArbzt0=; b=miD2bBPkTJefTj3JIDRrN4lH8h6MXNKObVzB/UrzJBJZ7sy79U1YroI9+cnfOZA8Za IasdHDXtyWPYMb6VSeyjmxGtIO4yLxEsKqjyAn9b0iqtqoBtJCEXZwHjvddSRzx+dqh0 O+kdsrVZ4NX6bpLcV9O1zUJr8YvNa+IX5OqyEQXl8gwR3RLaYeWfZOa695HE6/duCjS5 gSmi7ytNnlY6Gvnkun5hqDJwt+1pIPvscL/RFMqwo/bl+EhgYuc3kF//xYaVDZrAOQYP y/nXtR/f1uy7TSDEkhhjKYUZr5RDKUWyrTOXsl2tFPy6gGz1evTgHQrA0PX9zCzWAFo4 gErg== X-Gm-Message-State: AOAM530eHBLJeyoAZd0BKTta+CDOGcT7iUUHLT7t1dbyoC04edOfyd1t gCEl4OOSHJZatbEXtKug6NTWse5jwJqlCw== X-Google-Smtp-Source: ABdhPJwdLu7IqD4M1rKKG98o2wSTJCgvwDt8vAMV5pg9B7v5qNMqDrdmpPNQKJfGMLB9uxNpvSIXaw== X-Received: by 2002:a5d:43cc:: with SMTP id v12mr18022588wrr.215.1621248703243; Mon, 17 May 2021 03:51:43 -0700 (PDT) Received: from localhost.localdomain (31.red-83-51-215.dynamicip.rima-tde.net. [83.51.215.31]) by smtp.gmail.com with ESMTPSA id z8sm16706698wrw.74.2021.05.17.03.51.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 17 May 2021 03:51:42 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v7 00/23] cpu: Introduce SysemuCPUOps structure Date: Mon, 17 May 2021 12:51:17 +0200 Message-Id: <20210517105140.1062037-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x430.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.25, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Richard Henderson , Laurent Vivier , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, qemu-ppc@nongnu.org, Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Missing review: 2-5 (new) and 13 Hi, This series is inspired on Claudio TCG work. Instead of separate TCG from other accelerators, here we separate sysemu operations (system VS user). Since v6: - Rebased (3 targets removed, Claudio's target/i386 series merged) - Addressed Richard & David comments Since v5: - Rework patch 10 after Peter Maydell explanation on v3: https://www.mail-archive.com/qemu-devel@nongnu.org/msg800849.html Since v4: - Removed watchpoint patches (need more work) (Richard) - Merged patch 1 & 7 "Move CPUClass::vmsd to SysemuCPUOps" (Eduardo) - Reworded cpu_virtio_is_big_endian description (Greg) - Move write_elf() in target/riscv/cpu.c (rebased on top of 43a965888) - Added R-b tags Since v3: - SysemuCPUOps const (Richard) - added missing xtensa #ifdef'ry - added missing aa64/sve #ifdef'ry - added Laurent R-b Since v2: - fixed lm32/unicore32 - remove USER_ONLY ifdef'ry from "cpu.h" (Claudio) Since v1: - Name 'sysemu' (Claudio) - change each field progressively (Richard) $ git backport-diff Key: [----] : patches are identical [####] : number of functional differences between upstream/downstream patch [down] : patch is downstream-only The flags [FC] indicate (F)unctional and (C)ontextual differences, respective= ly 001/23:[down] 'NOTFORMERGE target/arm: Restrict MTE code to softmmu' 002/23:[down] 'cpu: Restrict target cpu_do_transaction_failed() handlers to s= ysemu' 003/23:[down] 'cpu: Restrict target cpu_do_unaligned_access() handlers to sys= emu' 004/23:[down] 'cpu: Remove duplicated 'sysemu/hw_accel.h' header' 005/23:[down] 'cpu: Split as cpu-common / cpu-sysemu' 006/23:[0002] [FC] 'cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from= _attrs' 007/23:[0010] [FC] 'cpu: Introduce cpu_virtio_is_big_endian()' 008/23:[0088] [FC] 'cpu: Directly use cpu_write_elf*() fallback handlers in p= lace' 009/23:[0022] [FC] 'cpu: Directly use get_paging_enabled() fallback handlers = in place' 010/23:[0026] [FC] 'cpu: Directly use get_memory_mapping() fallback handlers = in place' 011/23:[0007] [FC] 'cpu: Assert DeviceClass::vmsd is NULL on user emulation' 012/23:[0004] [FC] 'cpu: Rename CPUClass vmsd -> legacy_vmsd' 013/23:[down] 'cpu: Move AVR target vmsd field from CPUClass to DeviceClass' 014/23:[0014] [FC] 'cpu: Introduce SysemuCPUOps structure' 015/23:[0003] [FC] 'cpu: Move CPUClass::vmsd to SysemuCPUOps' 016/23:[0002] [FC] 'cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps' 017/23:[----] [--] 'cpu: Move CPUClass::get_crash_info to SysemuCPUOps' 018/23:[----] [-C] 'cpu: Move CPUClass::write_elf* to SysemuCPUOps' 019/23:[----] [--] 'cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps' 020/23:[0055] [FC] 'cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps' 021/23:[----] [--] 'cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps' 022/23:[----] [--] 'cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps' 023/23:[0012] [FC] 'cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c' Regards, Phil. Philippe Mathieu-Daud=C3=A9 (23): NOTFORMERGE target/arm: Restrict MTE code to softmmu cpu: Restrict target cpu_do_transaction_failed() handlers to sysemu cpu: Restrict target cpu_do_unaligned_access() handlers to sysemu cpu: Remove duplicated 'sysemu/hw_accel.h' header cpu: Split as cpu-common / cpu-sysemu cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs cpu: Introduce cpu_virtio_is_big_endian() cpu: Directly use cpu_write_elf*() fallback handlers in place cpu: Directly use get_paging_enabled() fallback handlers in place cpu: Directly use get_memory_mapping() fallback handlers in place cpu: Assert DeviceClass::vmsd is NULL on user emulation cpu: Rename CPUClass vmsd -> legacy_vmsd cpu: Move AVR target vmsd field from CPUClass to DeviceClass cpu: Introduce SysemuCPUOps structure cpu: Move CPUClass::vmsd to SysemuCPUOps cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps cpu: Move CPUClass::get_crash_info to SysemuCPUOps cpu: Move CPUClass::write_elf* to SysemuCPUOps cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c include/hw/core/cpu.h | 92 +++++--------------- include/hw/core/sysemu-cpu-ops.h | 92 ++++++++++++++++++++ include/migration/vmstate.h | 2 - target/alpha/cpu.h | 12 ++- target/arm/cpu.h | 9 +- target/arm/internals.h | 2 + target/avr/cpu.h | 1 + target/cris/cpu.h | 7 +- target/hexagon/cpu.h | 3 + target/hppa/cpu.h | 5 +- target/i386/cpu.h | 9 +- target/m68k/cpu.h | 10 ++- target/microblaze/cpu.h | 11 +-- target/mips/cpu.h | 3 + target/mips/tcg/tcg-internal.h | 6 +- target/nios2/cpu.h | 4 +- target/openrisc/cpu.h | 6 +- target/ppc/cpu.h | 5 +- target/ppc/internal.h | 2 + target/riscv/cpu.h | 21 +++-- target/rx/cpu.h | 5 ++ target/s390x/cpu.h | 3 + target/s390x/internal.h | 2 + target/sh4/cpu.h | 11 ++- target/sparc/cpu.h | 14 +-- target/tricore/cpu.h | 5 ++ target/xtensa/cpu.h | 19 ++-- cpu.c | 18 ++-- hw/core/{cpu.c =3D> cpu-common.c} | 116 ------------------------- hw/core/cpu-sysemu.c | 145 +++++++++++++++++++++++++++++++ hw/virtio/virtio.c | 4 +- stubs/vmstate.c | 2 - target/alpha/cpu.c | 8 +- target/arm/cpu.c | 18 ++-- target/arm/tlb_helper.c | 4 +- target/avr/cpu.c | 8 +- target/avr/machine.c | 4 +- target/cris/cpu.c | 8 +- target/hppa/cpu.c | 8 +- target/i386/cpu.c | 28 +++--- target/m68k/cpu.c | 8 +- target/microblaze/cpu.c | 8 +- target/microblaze/helper.c | 35 ++++---- target/mips/cpu.c | 10 ++- target/nios2/cpu.c | 8 +- target/openrisc/cpu.c | 8 +- target/ppc/excp_helper.c | 3 +- target/riscv/cpu.c | 14 ++- target/rx/cpu.c | 10 ++- target/s390x/cpu.c | 14 ++- target/sh4/cpu.c | 11 ++- target/sparc/cpu.c | 10 ++- target/sparc/ldst_helper.c | 5 +- target/tricore/cpu.c | 6 +- target/xtensa/cpu.c | 10 ++- target/ppc/translate_init.c.inc | 20 +++-- hw/core/meson.build | 3 +- target/arm/meson.build | 6 +- 58 files changed, 587 insertions(+), 334 deletions(-) create mode 100644 include/hw/core/sysemu-cpu-ops.h rename hw/core/{cpu.c =3D> cpu-common.c} (73%) create mode 100644 hw/core/cpu-sysemu.c --=20 2.26.3