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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id r2sm3916126wrv.39.2021.05.20.08.28.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 May 2021 08:28:41 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 0/9] target/arm: MVE preliminaries Date: Thu, 20 May 2021 16:28:31 +0100 Message-Id: <20210520152840.24453-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This patchset is a collection of easy preliminary MVE patches, which I send out now just to try to avoid the MVE patchset landing as one enormous series. These patches: * update feature checks on existing insns that should now check "if FP or MVE" rather than just "if FP" * fixes a minor non-guest-visible issue in fp_sysreg_checks() * adds support for reading and writing the MVE VPR register * makes FPSCR.LTPSIZE writable if MVE * makes FPSCR.QC exist for MVE None of this code will be "live" yet, as no CPU sets the MVE ID register fields. The last patch is not MVE related but I've had it kicking about in a private branch for a while now and it would be nice to have it upstream even though we don't have an immediate in-tree use. It just makes the NS VTOR configurable by the board/SoC the same way the S VTOR already is, which then matches the hardware. thanks -- PMM Peter Maydell (9): target/arm: Add isar feature check functions for MVE target/arm: Update feature checks for insns which are "MVE or FP" target/arm: Move fpsp/fpdp isar check into callers of do_vfp_2op_sp/dp target/arm: Add MVE check to VMOV_reg_sp and VMOV_reg_dp target/arm: Fix return values in fp_sysreg_checks() target/arm: Implement M-profile VPR register target/arm: Make FPSCR.LTPSIZE writable for MVE target/arm: Enable FPSCR.QC bit for MVE target/arm: Allow board models to specify initial NS VTOR include/hw/arm/armv7m.h | 2 + target/arm/cpu.h | 33 ++++++++- hw/arm/armv7m.c | 7 ++ target/arm/cpu.c | 10 +++ target/arm/machine.c | 20 ++++++ target/arm/translate-vfp.c | 140 ++++++++++++++++++++++++++----------- target/arm/vfp_helper.c | 12 ++-- 7 files changed, 179 insertions(+), 45 deletions(-)