[RFC,0/5] target/ppc: powerpc_excp improvements - part I

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Fabiano Rosas June 1, 2021, 9:46 p.m. UTC

This is my attempt at reducing the size of powerpc_excp and cleaning
it up a bit. It has two parts:

part I (this series) tackles the big switch statement that runs the
interrupt emulation code. Each interrupt now gets its own callback
function that is kept within QOM. The per-processor code still
registers the interrupts in a similar manner to what is done today and
powerpc_excp replaces its switch statement for a function call.

part II (still WIP: https://github.com/farosas/qemu/commits/powerpc_excp)
tries to make powerpc_excp processor agnostic by removing the excp_model
checks and moving processor-specific interrupt properties to
per-processor QOM classes.

I think it would be nice if we could at the end have separate
interrupts and interrupt model implementations. That way we could
start moving things into well defined per-processor files, CONFIGs,
etc.

(So far tested on x86 emulating P9 and compile-only 32-bit and
linux-user. I still need to gather some command lines for the older
cpus.)

Based-on: eb22196316ee653178ae517de83b490ad3636b91 # ppc-for-6.1

Fabiano Rosas (5):
  target/ppc: powerpc_excp: Move lpes code to where it is used
  target/ppc: powerpc_excp: Remove dump_syscall_vectored
  target/ppc: powerpc_excp: Consolidade TLB miss code
  target/ppc: powerpc_excp: Standardize arguments to interrupt code
  target/ppc: powerpc_excp: Move interrupt raising code to QOM

 target/ppc/cpu.h         |  29 +-
 target/ppc/cpu_init.c    | 640 +++++++++++++++++++------------------
 target/ppc/excp_helper.c | 670 +++++----------------------------------
 target/ppc/interrupts.c  | 638 +++++++++++++++++++++++++++++++++++++
 target/ppc/machine.c     |   2 +-
 target/ppc/meson.build   |   1 +
 target/ppc/ppc_intr.h    |  55 ++++
 target/ppc/translate.c   |   3 +-
 8 files changed, 1117 insertions(+), 921 deletions(-)
 create mode 100644 target/ppc/interrupts.c
 create mode 100644 target/ppc/ppc_intr.h

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2.29.2