| Message ID | 20210624105521.3964-1-zhiwei_liu@c-sky.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | target/riscv: support packed extension v0.9.4 | expand |
Patchew URL: https://patchew.org/QEMU/20210624105521.3964-1-zhiwei_liu@c-sky.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20210624105521.3964-1-zhiwei_liu@c-sky.com
Subject: [PATCH v3 00/37] target/riscv: support packed extension v0.9.4
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
* [new tag] patchew/20210624105521.3964-1-zhiwei_liu@c-sky.com -> patchew/20210624105521.3964-1-zhiwei_liu@c-sky.com
- [tag update] patchew/20210624110057.2398779-1-kraxel@redhat.com -> patchew/20210624110057.2398779-1-kraxel@redhat.com
Switched to a new branch 'test'
9b8479a target/riscv: configure and turn on packed extension from command line
a45d6c5 target/riscv: RV64 Only 32-bit Packing Instructions
407cee3 target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions
fc3b523 target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions
edcd5eb target/riscv: RV64 Only 32-bit Multiply & Add Instructions
b6cfe0b target/riscv: RV64 Only 32-bit Multiply Instructions
64f89a9 target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions
530eb0d target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions
a2cf3f0 target/riscv: RV64 Only SIMD 32-bit Shift Instructions
3c17d19 target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions
7c1677e target/riscv: Non-SIMD Miscellaneous Instructions
0f7c4bc target/riscv: 32-bit Computation Instructions
261a6cd target/riscv: Non-SIMD Q31 saturation ALU Instructions
9ad5f0e target/riscv: Non-SIMD Q15 saturation ALU Instructions
c431031 target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract Instructions
6c54d3f target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions
2146a16 target/riscv: 64-bit Add/Subtract Instructions
e9714d0 target/riscv: 8-bit Multiply with 32-bit Add Instructions
cbdec32 target/riscv: Partial-SIMD Miscellaneous Instructions
50cc545 target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions
4ae4970 target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions
5b89c3e target/riscv: Signed MSW 32x16 Multiply and Add Instructions
e22fe8e target/riscv: Signed MSW 32x32 Multiply and Add Instructions
debaecc target/riscv: 16-bit Packing Instructions
2fd15e5 target/riscv: 8-bit Unpacking Instructions
794a74f target/riscv: SIMD 8-bit Miscellaneous Instructions
c2335b3 target/riscv: SIMD 16-bit Miscellaneous Instructions
ee1ae43 target/riscv: SIMD 8-bit Multiply Instructions
9e59b92 target/riscv: SIMD 16-bit Multiply Instructions
115514d target/riscv: SIMD 8-bit Compare Instructions
cc55d93 target/riscv: SIMD 16-bit Compare Instructions
e757496 target/riscv: SIMD 8-bit Shift Instructions
2b52ff7 target/riscv: SIMD 16-bit Shift Instructions
e56faaa target/riscv: 8-bit Addition & Subtraction Instruction
2c34bbb target/riscv: 16-bit Addition & Subtraction Instructions
7bb9dfe target/riscv: Make the vector helper functions public
c3692b9 target/riscv: implementation-defined constant parameters
=== OUTPUT BEGIN ===
1/37 Checking commit c3692b9f2f20 (target/riscv: implementation-defined constant parameters)
2/37 Checking commit 7bb9dfe4b2a0 (target/riscv: Make the vector helper functions public)
3/37 Checking commit 2c34bbbccfb0 (target/riscv: 16-bit Addition & Subtraction Instructions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#100:
new file mode 100644
ERROR: space prohibited after that '*' (ctx:BxW)
#140: FILE: target/riscv/insn_trans/trans_rvp.c.inc:36:
+ void (* vecop)(TCGv, TCGv, TCGv),
^
ERROR: space prohibited after that '*' (ctx:BxW)
#141: FILE: target/riscv/insn_trans/trans_rvp.c.inc:37:
+ void (* op)(TCGv, TCGv, TCGv))
^
ERROR: space prohibited after that '*' (ctx:BxW)
#166: FILE: target/riscv/insn_trans/trans_rvp.c.inc:62:
+r_ool(DisasContext *ctx, arg_r *a, void (* fn)(TCGv, TCGv_ptr, TCGv, TCGv))
^
total: 3 errors, 1 warnings, 553 lines checked
Patch 3/37 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
4/37 Checking commit e56faaada505 (target/riscv: 8-bit Addition & Subtraction Instruction)
5/37 Checking commit 2b52ff7cb72a (target/riscv: SIMD 16-bit Shift Instructions)
ERROR: space prohibited after that '*' (ctx:BxW)
#100: FILE: target/riscv/insn_trans/trans_rvp.c.inc:144:
+ void (* fn)(TCGv, TCGv_ptr, TCGv, TCGv))
^
ERROR: space prohibited after that '*' (ctx:BxW)
#120: FILE: target/riscv/insn_trans/trans_rvp.c.inc:164:
+ void (* vecop)(TCGv, TCGv, target_long),
^
ERROR: space prohibited after that '*' (ctx:BxW)
#121: FILE: target/riscv/insn_trans/trans_rvp.c.inc:165:
+ void (* op)(TCGv, TCGv_ptr, TCGv, TCGv))
^
total: 3 errors, 0 warnings, 213 lines checked
Patch 5/37 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/37 Checking commit e757496fcc1e (target/riscv: SIMD 8-bit Shift Instructions)
7/37 Checking commit cc55d93120b9 (target/riscv: SIMD 16-bit Compare Instructions)
8/37 Checking commit 115514d7b76f (target/riscv: SIMD 8-bit Compare Instructions)
9/37 Checking commit 9e59b9255e0a (target/riscv: SIMD 16-bit Multiply Instructions)
ERROR: space prohibited after that '*' (ctx:BxW)
#91: FILE: target/riscv/insn_trans/trans_rvp.c.inc:253:
+ void (* fn)(TCGv_i64, TCGv_ptr, TCGv, TCGv))
^
total: 1 errors, 0 warnings, 199 lines checked
Patch 9/37 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/37 Checking commit ee1ae43ad525 (target/riscv: SIMD 8-bit Multiply Instructions)
11/37 Checking commit c2335b376114 (target/riscv: SIMD 16-bit Miscellaneous Instructions)
ERROR: space prohibited after that '*' (ctx:BxW)
#79: FILE: target/riscv/insn_trans/trans_rvp.c.inc:309:
+ void (* fn)(TCGv, TCGv_ptr, TCGv))
^
total: 1 errors, 0 warnings, 233 lines checked
Patch 11/37 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
12/37 Checking commit 794a74f89948 (target/riscv: SIMD 8-bit Miscellaneous Instructions)
13/37 Checking commit 2fd15e5fcbab (target/riscv: 8-bit Unpacking Instructions)
14/37 Checking commit debaecc03244 (target/riscv: 16-bit Packing Instructions)
15/37 Checking commit e22fe8e7daf1 (target/riscv: Signed MSW 32x32 Multiply and Add Instructions)
ERROR: space prohibited after that '*' (ctx:BxW)
#69: FILE: target/riscv/insn_trans/trans_rvp.c.inc:379:
+ void (* fn)(TCGv, TCGv_ptr, TCGv, TCGv, TCGv))
^
total: 1 errors, 0 warnings, 183 lines checked
Patch 15/37 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
16/37 Checking commit 5b89c3e249dd (target/riscv: Signed MSW 32x16 Multiply and Add Instructions)
17/37 Checking commit 4ae49704c503 (target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions)
18/37 Checking commit 50cc5450936e (target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions)
ERROR: space prohibited after that '*' (ctx:BxW)
#50: FILE: target/riscv/insn_trans/trans_rvp.c.inc:458:
+ void (* fn)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv))
^
total: 1 errors, 0 warnings, 92 lines checked
Patch 18/37 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
19/37 Checking commit cbdec3263aeb (target/riscv: Partial-SIMD Miscellaneous Instructions)
20/37 Checking commit e9714d03ed9a (target/riscv: 8-bit Multiply with 32-bit Add Instructions)
21/37 Checking commit 2146a16b28a5 (target/riscv: 64-bit Add/Subtract Instructions)
ERROR: space prohibited after that '*' (ctx:BxW)
#71: FILE: target/riscv/insn_trans/trans_rvp.c.inc:526:
+ void (* fn)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
^
total: 1 errors, 0 warnings, 240 lines checked
Patch 21/37 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
22/37 Checking commit 6c54d3fa42f8 (target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions)
ERROR: space prohibited after that '*' (ctx:BxW)
#67: FILE: target/riscv/insn_trans/trans_rvp.c.inc:599:
+ void (* fn)(TCGv_i64, TCGv_ptr, TCGv, TCGv, TCGv_i64))
^
total: 1 errors, 0 warnings, 252 lines checked
Patch 22/37 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
23/37 Checking commit c431031c7b1c (target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract Instructions)
24/37 Checking commit 9ad5f0e7df6d (target/riscv: Non-SIMD Q15 saturation ALU Instructions)
25/37 Checking commit 261a6cd03694 (target/riscv: Non-SIMD Q31 saturation ALU Instructions)
26/37 Checking commit 0f7c4bc1e41e (target/riscv: 32-bit Computation Instructions)
27/37 Checking commit 7c1677e7d344 (target/riscv: Non-SIMD Miscellaneous Instructions)
ERROR: space prohibited after that '*' (ctx:BxW)
#103: FILE: target/riscv/insn_trans/trans_rvp.c.inc:721:
+ void (* fn)(TCGv, TCGv_ptr, TCGv_i64, TCGv))
^
ERROR: space prohibited after that '*' (ctx:BxW)
#151: FILE: target/riscv/insn_trans/trans_rvp.c.inc:769:
+ void (* fn)(TCGv, TCGv_ptr, TCGv_i64, TCGv))
^
total: 2 errors, 0 warnings, 376 lines checked
Patch 27/37 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
28/37 Checking commit 3c17d19461f3 (target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions)
ERROR: space prohibited after that '*' (ctx:BxW)
#121: FILE: target/riscv/insn_trans/trans_rvp.c.inc:969:
+ void (* fn)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
^
total: 1 errors, 0 warnings, 433 lines checked
Patch 28/37 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
29/37 Checking commit a2cf3f09cb66 (target/riscv: RV64 Only SIMD 32-bit Shift Instructions)
ERROR: space prohibited after that '*' (ctx:BxW)
#71: FILE: target/riscv/insn_trans/trans_rvp.c.inc:1040:
+ void (* fn)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
^
total: 1 errors, 0 warnings, 195 lines checked
Patch 29/37 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
30/37 Checking commit 530eb0db6702 (target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions)
31/37 Checking commit 64f89a9d4f71 (target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions)
32/37 Checking commit b6cfe0b72c58 (target/riscv: RV64 Only 32-bit Multiply Instructions)
33/37 Checking commit edcd5ebd6867 (target/riscv: RV64 Only 32-bit Multiply & Add Instructions)
34/37 Checking commit fc3b5236ff09 (target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions)
35/37 Checking commit 407cee3b94a2 (target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions)
36/37 Checking commit a45d6c547896 (target/riscv: RV64 Only 32-bit Packing Instructions)
37/37 Checking commit 9b8479ad649d (target/riscv: configure and turn on packed extension from command line)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20210624105521.3964-1-zhiwei_liu@c-sky.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
On Thu, Jun 24, 2021 at 9:14 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: > > This patchset implements the packed extension for RISC-V on QEMU. > > You can also find this patch set on my > repo(https://github.com/romanheros/qemu.git branch:packed-upstream-v3). > > Features: > * support specification packed extension > v0.9.4(https://github.com/riscv/riscv-p-spec/) > * support basic packed extension. > * support Zpsoperand. There is now a 0.9.5, do you have plans to support that? Alistair > > v3: > * split 32 bit vector operations. > > v2: > * remove all the TARGET_RISCV64 macro. > * use tcg_gen_vec_* to accelabrate. > * update specficication to latest v0.9.4 > * fix kmsxda32, kmsda32,kslra32,smal > > LIU Zhiwei (37): > target/riscv: implementation-defined constant parameters > target/riscv: Make the vector helper functions public > target/riscv: 16-bit Addition & Subtraction Instructions > target/riscv: 8-bit Addition & Subtraction Instruction > target/riscv: SIMD 16-bit Shift Instructions > target/riscv: SIMD 8-bit Shift Instructions > target/riscv: SIMD 16-bit Compare Instructions > target/riscv: SIMD 8-bit Compare Instructions > target/riscv: SIMD 16-bit Multiply Instructions > target/riscv: SIMD 8-bit Multiply Instructions > target/riscv: SIMD 16-bit Miscellaneous Instructions > target/riscv: SIMD 8-bit Miscellaneous Instructions > target/riscv: 8-bit Unpacking Instructions > target/riscv: 16-bit Packing Instructions > target/riscv: Signed MSW 32x32 Multiply and Add Instructions > target/riscv: Signed MSW 32x16 Multiply and Add Instructions > target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions > target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions > target/riscv: Partial-SIMD Miscellaneous Instructions > target/riscv: 8-bit Multiply with 32-bit Add Instructions > target/riscv: 64-bit Add/Subtract Instructions > target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions > target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract > Instructions > target/riscv: Non-SIMD Q15 saturation ALU Instructions > target/riscv: Non-SIMD Q31 saturation ALU Instructions > target/riscv: 32-bit Computation Instructions > target/riscv: Non-SIMD Miscellaneous Instructions > target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions > target/riscv: RV64 Only SIMD 32-bit Shift Instructions > target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions > target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions > target/riscv: RV64 Only 32-bit Multiply Instructions > target/riscv: RV64 Only 32-bit Multiply & Add Instructions > target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions > target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions > target/riscv: RV64 Only 32-bit Packing Instructions > target/riscv: configure and turn on packed extension from command line > > target/riscv/cpu.c | 34 + > target/riscv/cpu.h | 6 + > target/riscv/helper.h | 330 ++ > target/riscv/insn32.decode | 370 +++ > target/riscv/insn_trans/trans_rvp.c.inc | 1155 +++++++ > target/riscv/internals.h | 50 + > target/riscv/meson.build | 1 + > target/riscv/packed_helper.c | 3851 +++++++++++++++++++++++ > target/riscv/translate.c | 3 + > target/riscv/vector_helper.c | 82 +- > 10 files changed, 5824 insertions(+), 58 deletions(-) > create mode 100644 target/riscv/insn_trans/trans_rvp.c.inc > create mode 100644 target/riscv/packed_helper.c > > -- > 2.17.1 > >
On 2021/7/1 上午9:30, Alistair Francis wrote: > On Thu, Jun 24, 2021 at 9:14 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote: >> This patchset implements the packed extension for RISC-V on QEMU. >> >> You can also find this patch set on my >> repo(https://github.com/romanheros/qemu.git branch:packed-upstream-v3). >> >> Features: >> * support specification packed extension >> v0.9.4(https://github.com/riscv/riscv-p-spec/) >> * support basic packed extension. >> * support Zpsoperand. > There is now a 0.9.5, do you have plans to support that? Thanks for pointing it out. After review the latest change, I think it is small change. So I will not update the implementation to v0.9.5. I hope next supporting version is v1.0. Thanks, Zhiwei > > Alistair > >> v3: >> * split 32 bit vector operations. >> >> v2: >> * remove all the TARGET_RISCV64 macro. >> * use tcg_gen_vec_* to accelabrate. >> * update specficication to latest v0.9.4 >> * fix kmsxda32, kmsda32,kslra32,smal >> >> LIU Zhiwei (37): >> target/riscv: implementation-defined constant parameters >> target/riscv: Make the vector helper functions public >> target/riscv: 16-bit Addition & Subtraction Instructions >> target/riscv: 8-bit Addition & Subtraction Instruction >> target/riscv: SIMD 16-bit Shift Instructions >> target/riscv: SIMD 8-bit Shift Instructions >> target/riscv: SIMD 16-bit Compare Instructions >> target/riscv: SIMD 8-bit Compare Instructions >> target/riscv: SIMD 16-bit Multiply Instructions >> target/riscv: SIMD 8-bit Multiply Instructions >> target/riscv: SIMD 16-bit Miscellaneous Instructions >> target/riscv: SIMD 8-bit Miscellaneous Instructions >> target/riscv: 8-bit Unpacking Instructions >> target/riscv: 16-bit Packing Instructions >> target/riscv: Signed MSW 32x32 Multiply and Add Instructions >> target/riscv: Signed MSW 32x16 Multiply and Add Instructions >> target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions >> target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions >> target/riscv: Partial-SIMD Miscellaneous Instructions >> target/riscv: 8-bit Multiply with 32-bit Add Instructions >> target/riscv: 64-bit Add/Subtract Instructions >> target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions >> target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract >> Instructions >> target/riscv: Non-SIMD Q15 saturation ALU Instructions >> target/riscv: Non-SIMD Q31 saturation ALU Instructions >> target/riscv: 32-bit Computation Instructions >> target/riscv: Non-SIMD Miscellaneous Instructions >> target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions >> target/riscv: RV64 Only SIMD 32-bit Shift Instructions >> target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions >> target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions >> target/riscv: RV64 Only 32-bit Multiply Instructions >> target/riscv: RV64 Only 32-bit Multiply & Add Instructions >> target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions >> target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions >> target/riscv: RV64 Only 32-bit Packing Instructions >> target/riscv: configure and turn on packed extension from command line >> >> target/riscv/cpu.c | 34 + >> target/riscv/cpu.h | 6 + >> target/riscv/helper.h | 330 ++ >> target/riscv/insn32.decode | 370 +++ >> target/riscv/insn_trans/trans_rvp.c.inc | 1155 +++++++ >> target/riscv/internals.h | 50 + >> target/riscv/meson.build | 1 + >> target/riscv/packed_helper.c | 3851 +++++++++++++++++++++++ >> target/riscv/translate.c | 3 + >> target/riscv/vector_helper.c | 82 +- >> 10 files changed, 5824 insertions(+), 58 deletions(-) >> create mode 100644 target/riscv/insn_trans/trans_rvp.c.inc >> create mode 100644 target/riscv/packed_helper.c >> >> -- >> 2.17.1 >> >>
This patchset implements the packed extension for RISC-V on QEMU. You can also find this patch set on my repo(https://github.com/romanheros/qemu.git branch:packed-upstream-v3). Features: * support specification packed extension v0.9.4(https://github.com/riscv/riscv-p-spec/) * support basic packed extension. * support Zpsoperand. v3: * split 32 bit vector operations. v2: * remove all the TARGET_RISCV64 macro. * use tcg_gen_vec_* to accelabrate. * update specficication to latest v0.9.4 * fix kmsxda32, kmsda32,kslra32,smal LIU Zhiwei (37): target/riscv: implementation-defined constant parameters target/riscv: Make the vector helper functions public target/riscv: 16-bit Addition & Subtraction Instructions target/riscv: 8-bit Addition & Subtraction Instruction target/riscv: SIMD 16-bit Shift Instructions target/riscv: SIMD 8-bit Shift Instructions target/riscv: SIMD 16-bit Compare Instructions target/riscv: SIMD 8-bit Compare Instructions target/riscv: SIMD 16-bit Multiply Instructions target/riscv: SIMD 8-bit Multiply Instructions target/riscv: SIMD 16-bit Miscellaneous Instructions target/riscv: SIMD 8-bit Miscellaneous Instructions target/riscv: 8-bit Unpacking Instructions target/riscv: 16-bit Packing Instructions target/riscv: Signed MSW 32x32 Multiply and Add Instructions target/riscv: Signed MSW 32x16 Multiply and Add Instructions target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions target/riscv: Partial-SIMD Miscellaneous Instructions target/riscv: 8-bit Multiply with 32-bit Add Instructions target/riscv: 64-bit Add/Subtract Instructions target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract Instructions target/riscv: Non-SIMD Q15 saturation ALU Instructions target/riscv: Non-SIMD Q31 saturation ALU Instructions target/riscv: 32-bit Computation Instructions target/riscv: Non-SIMD Miscellaneous Instructions target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions target/riscv: RV64 Only SIMD 32-bit Shift Instructions target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions target/riscv: RV64 Only 32-bit Multiply Instructions target/riscv: RV64 Only 32-bit Multiply & Add Instructions target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions target/riscv: RV64 Only 32-bit Packing Instructions target/riscv: configure and turn on packed extension from command line target/riscv/cpu.c | 34 + target/riscv/cpu.h | 6 + target/riscv/helper.h | 330 ++ target/riscv/insn32.decode | 370 +++ target/riscv/insn_trans/trans_rvp.c.inc | 1155 +++++++ target/riscv/internals.h | 50 + target/riscv/meson.build | 1 + target/riscv/packed_helper.c | 3851 +++++++++++++++++++++++ target/riscv/translate.c | 3 + target/riscv/vector_helper.c | 82 +- 10 files changed, 5824 insertions(+), 58 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvp.c.inc create mode 100644 target/riscv/packed_helper.c