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target/arm: MVE slices 3 and 4
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[for-6.2,00/53] target/arm: MVE slices 3 and 4
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[for-6.2,01/53] target/arm: Note that we handle VMOVL as a special case of VSHLL
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[for-6.2,02/53] target/arm: Print MVE VPR in CPU dumps
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[for-6.2,03/53] target/arm: Fix MVE VSLI by 0 and VSRI by <dt>
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[for-6.2,04/53] target/arm: Fix signed VADDV
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[for-6.2,05/53] target/arm: Fix mask handling for MVE narrowing operations
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[for-6.2,06/53] target/arm: Fix 48-bit saturating shifts
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[for-6.2,07/53] target/arm: Fix MVE 48-bit SQRSHRL for small right shifts
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[for-6.2,08/53] target/arm: Fix calculation of LTP mask when LR is 0
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[for-6.2,09/53] target/arm: Factor out mve_eci_mask()
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[for-6.2,10/53] target/arm: Fix VPT advance when ECI is non-zero
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[for-6.2,11/53] target/arm: Fix VLDRB/H/W for predicated elements
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[for-6.2,12/53] target/arm: Implement MVE VMULL (polynomial)
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[for-6.2,13/53] target/arm: Implement MVE incrementing/decrementing dup insns
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[for-6.2,14/53] target/arm: Factor out gen_vpst()
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[for-6.2,15/53] target/arm: Implement MVE integer vector comparisons
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[for-6.2,16/53] target/arm: Implement MVE integer vector-vs-scalar comparisons
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[for-6.2,17/53] target/arm: Implement MVE VPSEL
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[for-6.2,18/53] target/arm: Implement MVE VMLAS
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[for-6.2,19/53] target/arm: Implement MVE shift-by-scalar
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[for-6.2,20/53] target/arm: Move 'x' and 'a' bit definitions into vmlaldav formats
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[for-6.2,21/53] target/arm: Implement MVE integer min/max across vector
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[for-6.2,22/53] target/arm: Implement MVE VABAV
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[for-6.2,23/53] target/arm: Implement MVE narrowing moves
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[for-6.2,24/53] target/arm: Rename MVEGenDualAccOpFn to MVEGenLongDualAccOpFn
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[for-6.2,25/53] target/arm: Implement MVE VMLADAV and VMLSLDAV
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[for-6.2,26/53] target/arm: Implement MVE VMLA
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[for-6.2,27/53] target/arm: Implement MVE saturating doubling multiply accumulates
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[for-6.2,28/53] target/arm: Implement MVE VQABS, VQNEG
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[for-6.2,29/53] target/arm: Implement MVE VMAXA, VMINA
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[for-6.2,30/53] target/arm: Implement MVE VMOV to/from 2 general-purpose registers
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[for-6.2,31/53] target/arm: Implement MVE VPNOT
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[for-6.2,32/53] target/arm: Implement MVE VCTP
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[for-6.2,33/53] target/arm: Implement MVE scatter-gather insns
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[for-6.2,34/53] target/arm: Implement MVE scatter-gather immediate forms
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[for-6.2,35/53] target/arm: Implement MVE interleaving loads/stores
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[for-6.2,36/53] target/arm: Implement MVE VADD (floating-point)
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[for-6.2,37/53] target/arm: Implement MVE VSUB, VMUL, VABD, VMAXNM, VMINNM
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[for-6.2,38/53] target/arm: Implement MVE VCADD
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[for-6.2,39/53] target/arm: Implement MVE VFMA and VFMS
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[for-6.2,40/53] target/arm: Implement MVE VCMUL and VCMLA
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[for-6.2,41/53] target/arm: Implement MVE VMAXNMA and VMINNMA
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[for-6.2,42/53] target/arm: Implement MVE scalar fp insns
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[for-6.2,43/53] target/arm: Implement MVE fp-with-scalar VFMA, VFMAS
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[for-6.2,44/53] softfloat: Remove assertion preventing silencing of NaN in default-NaN mode
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[for-6.2,45/53] target/arm: Implement MVE FP max/min across vector
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[for-6.2,46/53] target/arm: Implement MVE fp vector comparisons
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[for-6.2,47/53] target/arm: Implement MVE fp scalar comparisons
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[for-6.2,48/53] target/arm: Implement MVE VCVT between floating and fixed point
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[for-6.2,49/53] target/arm: Implement MVE VCVT between fp and integer
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[for-6.2,50/53] target/arm: Implement MVE VCVT with specified rounding mode
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[for-6.2,51/53] target/arm: Implement MVE VCVT between single and half precision
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[for-6.2,52/53] target/arm: Implement MVE VRINT insns
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[for-6.2,53/53] target/arm: Enable MVE in Cortex-M55
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