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Fri, 22 Oct 2021 11:19:20 -0700 (PDT) From: Alexey Baturo X-Google-Original-From: Alexey Baturo To: Subject: [PATCH v16 0/8] RISC-V Pointer Masking implementation Date: Fri, 22 Oct 2021 21:19:02 +0300 Message-Id: <20211022181910.1999197-1-space.monkey.delivers@gmail.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=baturo.alexey@gmail.com; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: baturo.alexey@gmail.com, qemu-riscv@nongnu.org, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, richard.henderson@linaro.org, qemu-devel@nongnu.org, space.monkey.delivers@gmail.com, Alistair.Francis@wdc.com, kupokupokupopo@gmail.com, palmer@dabbelt.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" v15: Renamed pm into pointer_masking in machine state. v14: Addressed Richard's comments from previous series. v13: Rebased QEMU and addressed Richard's comment. v12: Updated function for adjusting address with pointer masking to allocate and use temp register. v11: Addressed a few style issues Alistair mentioned in the previous review. If this patch series would be accepted, I think my further attention would be to: - Support pm for memory operations for RVV - Add proper csr and support pm for memory operations for Hypervisor mode - Support address wrapping on unaligned accesses as @Richard mentioned previously Thanks! Alexey Baturo (7): [RISCV_PM] Add J-extension into RISC-V [RISCV_PM] Add CSR defines for RISC-V PM extension [RISCV_PM] Support CSRs required for RISC-V PM extension except for the h-mode [RISCV_PM] Add J extension state description [RISCV_PM] Print new PM CSRs in QEMU logs [RISCV_PM] Support pointer masking for RISC-V for i/c/f/d/a types of instructions [RISCV_PM] Allow experimental J-ext to be turned on Anatoly Parshintsev (1): [RISCV_PM] Implement address masking functions required for RISC-V Pointer Masking extension target/riscv/cpu.c | 13 ++ target/riscv/cpu.h | 15 ++ target/riscv/cpu_bits.h | 96 ++++++++ target/riscv/cpu_helper.c | 18 ++ target/riscv/csr.c | 285 ++++++++++++++++++++++++ target/riscv/insn_trans/trans_rva.c.inc | 3 + target/riscv/insn_trans/trans_rvd.c.inc | 2 + target/riscv/insn_trans/trans_rvf.c.inc | 2 + target/riscv/insn_trans/trans_rvi.c.inc | 2 + target/riscv/machine.c | 27 +++ target/riscv/translate.c | 43 ++++ 11 files changed, 506 insertions(+)