[v17,0/8] RISC-V Pointer Masking implementation

Message

Alexey Baturo Oct. 25, 2021, 5:36 p.m. UTC

v16:
Rebased against the latest tree

v15:
Renamed pm into pointer_masking in machine state.

v14:
Addressed Richard's comments from previous series.

v13:
Rebased QEMU and addressed Richard's comment.

v12:
Updated function for adjusting address with pointer masking to allocate and use temp register.

v11:
Addressed a few style issues Alistair mentioned in the previous review.

Alexey Baturo (7):
  target/riscv: Add J-extension into RISC-V
  target/riscv: Add CSR defines for RISC-V PM extension
  target/riscv: Support CSRs required for RISC-V PM extension except for
    the h-mode
  target/riscv: Add J extension state description
  target/riscv: Print new PM CSRs in QEMU logs
  target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types
    of instructions
  target/riscv: Allow experimental J-ext to be turned on

Anatoly Parshintsev (1):
  target/riscv: Implement address masking functions required for RISC-V
    Pointer Masking extension

 target/riscv/cpu.c                      |  13 ++
 target/riscv/cpu.h                      |  15 ++
 target/riscv/cpu_bits.h                 |  96 ++++++++
 target/riscv/cpu_helper.c               |  18 ++
 target/riscv/csr.c                      | 285 ++++++++++++++++++++++++
 target/riscv/insn_trans/trans_rva.c.inc |   3 +
 target/riscv/insn_trans/trans_rvd.c.inc |   2 +
 target/riscv/insn_trans/trans_rvf.c.inc |   2 +
 target/riscv/insn_trans/trans_rvi.c.inc |   2 +
 target/riscv/machine.c                  |  27 +++
 target/riscv/translate.c                |  43 ++++
 11 files changed, 506 insertions(+)