From patchwork Tue Dec 21 05:40:34 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: WANG Xuerui X-Patchwork-Id: 12689037 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 59D55C433EF for ; Tue, 21 Dec 2021 05:42:50 +0000 (UTC) Received: from localhost ([::1]:43730 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1mzXvF-0000wi-0Y for qemu-devel@archiver.kernel.org; Tue, 21 Dec 2021 00:42:49 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48240) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mzXts-0007sJ-Si for qemu-devel@nongnu.org; Tue, 21 Dec 2021 00:41:24 -0500 Received: from mail.xen0n.name ([115.28.160.31]:56278 helo=mailbox.box.xen0n.name) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1mzXto-0001sG-Sk for qemu-devel@nongnu.org; Tue, 21 Dec 2021 00:41:24 -0500 Received: from ld50.lan (unknown [101.88.31.179]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by mailbox.box.xen0n.name (Postfix) with ESMTPSA id 18886600B5; Tue, 21 Dec 2021 13:41:08 +0800 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=xen0n.name; s=mail; t=1640065268; bh=bpXdXSQGtnePPC5ds8jBdQ9rZHShEvxcKbOwwUf0tyg=; h=From:To:Cc:Subject:Date:From; b=QdIltY2fvG8tavy43FXFNFYmMsyNI49J/Um71JoeeyxYxT+YldbCQrRvvfCyDQeOm 9tsGKuIbkNeBx4F8qfCWRQHarz3qSI35XESy6sc2cH+b2n0tFgpvcGZi+RKQPRb2Ko xnJTqL4g2284gnCUpjDXR/FiFMW4al6mb6ObJSYc= From: WANG Xuerui To: qemu-devel@nongnu.org Subject: [PATCH v11 00/31] LoongArch64 port of QEMU TCG Date: Tue, 21 Dec 2021 13:40:34 +0800 Message-Id: <20211221054105.178795-1-git@xen0n.name> X-Mailer: git-send-email 2.34.0 MIME-Version: 1.0 Received-SPF: pass client-ip=115.28.160.31; envelope-from=git@xen0n.name; helo=mailbox.box.xen0n.name X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , XiaoJuan Yang , Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Laurent Vivier , WANG Xuerui , =?utf-8?q?Alex_Benn=C3=A9e?= , Song Gao Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi all, This is a port of QEMU TCG to the brand-new CPU architecture LoongArch, introduced by Loongson with their 3A5000 chips. Everything is tested on real 3A5000 board (system emulation, linux-user, make check) and GitLab (CI jobs), and rebased to latest master branch. ## About the series Only the LP64D ABI is supported, as this is the only one fully implemented and supported by Loongson so far. 32-bit support is incomplete from outset, and removed from the very latest upstream submissions, so you can't even configure for that. The architecture's documentation is already translated into English; it can be browsed at https://loongson.github.io/LoongArch-Documentation/. The LoongArch ELF psABI doc (version 1.00) could be found at [1]; if anything is missing there, it's most likely the same as RISC-V, but you can always raise an issue over their issue tracker at [2]. [1]: https://loongson.github.io/LoongArch-Documentation/LoongArch-ELF-ABI-EN.html [2]: https://github.com/loongson/LoongArch-Documentation/issues In this series I made use of generated instruction encodings and emitters from https://github.com/loongson-community/loongarch-opcodes (a community project started by myself, something I must admit), as the LoongArch encoding is highly irregular even for a fixed 32-bit ISA, and I want to minimize the maintenance burden for future collaboration. This series touches some of the same files as Song Gao's previous submission of LoongArch *target* support, which is a bit unfortunate; one of us will have to rebase after either series gets in. Actual conflict should only happen on build system bits and include/elf.h, though, as we're working on entirely different areas. ## How to build and test this Upstream support for LoongArch is largely WIP for now, which means you must apply a lot of patches if you want to even cross-build for this arch. The main sources I used are as follows: * binutils: (already upstream as of November 2021) * gcc: https://github.com/xen0n/gcc/tree/for-gentoo-gcc-12-v5 based on https://github.com/loongson/gcc/tree/loongarch_upstream_v3 * glibc: https://github.com/xen0n/glibc/tree/for-gentoo-glibc-2.34-v3 based on https://github.com/loongson/glibc/tree/loongarch_2_34_dev * Linux: https://github.com/xen0n/linux/tree/loongarch-playground-v7 based on https://github.com/loongson/linux/tree/loongarch-next * Gentoo overlay: https://github.com/xen0n/loongson-overlay I have made ready-to-use Gentoo stage3 tarballs, but they're served with CDN off my personal cloud account, and I don't want the link to be exposed so that my bills skyrocket; you can reach me off-list to get the links if you're interested. As for the hardware availability, the boards can already be bought in China on Taobao, and I think some people at Loongson might be able to arrange for testing environments, if testing on real hardware other than mine is required before merging; they have their in-house Debian spin-off from the early days of this architecture. Their kernel is ABI-incompatible with the version being upstreamed and used by me, but QEMU should work there regardless. Lastly, I'm new to QEMU development and this is my first patch series here; apologizes if I get anything wrong, and any help or suggestion is certainly appreciated! ## Changelog v11 -> v10: - Rebased to latest development branch v10 -> v9: - Collected Reviewed-by tags from last round - Fixed Patch 28's register allocation for &signal_pending and added explanatory comments per review - Updated Docker image - Updated a couple of places still mentioning the "LP64" ABI (properly disambiguated into LP64S/LP64F/LP64D in the latest ABI spec) to say "LP64*" instead v9 -> v8: - Rebased on top of Richard's lu-safesignal branch for eventual merge v8 -> v7: - Rebased to latest development branch - Adjusted component field of Patch 29's subject line to say "linux-user" after rebase - Adjusted Patch 31 slightly according to review (you can check out the Patchew diff between revisions for details) v7 -> v6: - Rebased to latest development branch - Added Docker image for cross-compilation and cross-build CI jobs v6 -> v5: - Fixed many places using 0/1 to say false/true - Tweaks to tcg_out_movi - Moved variable declarations to top of function, as per QEMU coding style - Added ASCII art to better explain names like `hi12` `hi32` and `hi52` - Added example `uname -a` outputs to commit message of Patch 30 to help people make sense of the change v5 -> v4: - Updated generated instruction definition to latest (added ldx/stx family of indexed load/stores) - Incorporated Richard's suggestion for tcg_out_movi, tested to cover the cases it's supposed to improve - Fixed a "size == MO_64" occurrence to just say "type" - Used indexed load/stores to optimize qemu_ld/st - Fixed zero-extension of address register for qemu_ld/st on 32-bit targets v4 -> v3: - Addressed all review comments from v3 - Made MAX_CODE_GEN_BUFFER_SIZE to be just SIZE_MAX (but kept TCG_TARGET_NB_REGS as macro definition) - Updated generated instruction definition, made it clear that the whole file is generated - Used deposit64 for hand-written relocation code - Reworked tcg_out_movi - Use pcalau12i + ori for PC-relative values whose offset fits in 32-bit - Every individual insn in the slow path (lu12i.w + ori + cu32i.d + cu52i.d) can be suppressed if not needed - Fixed constraint of setcond ops, don't allow constant zero for 1st operand v3 -> v2: - Addressed all review comments from v2 - Re-organized changes to tcg-target.h so that it's incrementally updated in each commit implementing ops - Removed support for the eqv op - Added support for bswap16_i{32,64} ops - Fixed and refactored various places as pointed out during review - Updated generated instruction definitions to latest v2 -> v1: - Addressed all review comments from v1 - Use "loongarch64" everywhere, tcg directory renamed to "tcg/loongarch64" - Removed all redundant TCG_TARGET_REG_BITS conditional - Removed support for the neg op - Added support for eqv and bswap32_i64 ops - Added safe syscall handling for linux-user - Fixed everything else I could see - Updated generated instruction definitions to latest - Reordered the configure/meson.build changes to come last v10: https://patchew.org/QEMU/20211215125136.3449717-1-git@xen0n.name/ v9: https://patchew.org/QEMU/20211214080154.196350-1-git@xen0n.name/ v8: https://patchew.org/QEMU/20211124183231.1503090-1-git@xen0n.name/ v7: https://patchew.org/QEMU/20211122104201.112695-1-git@xen0n.name/ v6: https://patchew.org/QEMU/20210925173032.2434906-1-git@xen0n.name/ v5: https://patchew.org/QEMU/20210924172527.904294-1-git@xen0n.name/ v4: https://patchew.org/QEMU/20210923165939.729081-1-git@xen0n.name/ v3: https://patchew.org/QEMU/20210922180927.666273-1-git@xen0n.name/ v2: https://patchew.org/QEMU/20210921201915.601245-1-git@xen0n.name/ v1: https://patchew.org/QEMU/20210920080451.408655-1-git@xen0n.name/ WANG Xuerui (31): elf: Add machine type value for LoongArch MAINTAINERS: Add tcg/loongarch64 entry with myself as maintainer tcg/loongarch64: Add the tcg-target.h file tcg/loongarch64: Add generated instruction opcodes and encoding helpers tcg/loongarch64: Add register names, allocation order and input/output sets tcg/loongarch64: Define the operand constraints tcg/loongarch64: Implement necessary relocation operations tcg/loongarch64: Implement the memory barrier op tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi tcg/loongarch64: Implement goto_ptr tcg/loongarch64: Implement sign-/zero-extension ops tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc ops tcg/loongarch64: Implement deposit/extract ops tcg/loongarch64: Implement bswap{16,32,64} ops tcg/loongarch64: Implement clz/ctz ops tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops tcg/loongarch64: Implement add/sub ops tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops tcg/loongarch64: Implement br/brcond ops tcg/loongarch64: Implement setcond ops tcg/loongarch64: Implement tcg_out_call tcg/loongarch64: Implement simple load/store ops tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops tcg/loongarch64: Implement tcg_target_qemu_prologue tcg/loongarch64: Implement exit_tb/goto_tb tcg/loongarch64: Implement tcg_target_init tcg/loongarch64: Register the JIT common-user: Add safe syscall handling for loongarch64 hosts linux-user: Implement CPU-specific signal handler for loongarch64 hosts configure, meson.build: Mark support for loongarch64 hosts tests/docker: Add gentoo-loongarch64-cross image and run cross builds in GitLab .gitlab-ci.d/container-cross.yml | 27 + .gitlab-ci.d/crossbuilds.yml | 19 + MAINTAINERS | 7 + .../host/loongarch64/safe-syscall.inc.S | 90 + configure | 5 + include/elf.h | 2 + linux-user/host/loongarch64/host-signal.h | 87 + meson.build | 2 +- tcg/loongarch64/tcg-insn-defs.c.inc | 979 ++++++++++ tcg/loongarch64/tcg-target-con-set.h | 31 + tcg/loongarch64/tcg-target-con-str.h | 28 + tcg/loongarch64/tcg-target.c.inc | 1677 +++++++++++++++++ tcg/loongarch64/tcg-target.h | 180 ++ tests/docker/Makefile.include | 21 + .../gentoo-loongarch64-cross.docker | 21 + .../build-toolchain.sh | 128 ++ 16 files changed, 3303 insertions(+), 1 deletion(-) create mode 100644 common-user/host/loongarch64/safe-syscall.inc.S create mode 100644 linux-user/host/loongarch64/host-signal.h create mode 100644 tcg/loongarch64/tcg-insn-defs.c.inc create mode 100644 tcg/loongarch64/tcg-target-con-set.h create mode 100644 tcg/loongarch64/tcg-target-con-str.h create mode 100644 tcg/loongarch64/tcg-target.c.inc create mode 100644 tcg/loongarch64/tcg-target.h create mode 100644 tests/docker/dockerfiles/gentoo-loongarch64-cross.docker create mode 100755 tests/docker/dockerfiles/gentoo-loongarch64-cross.docker.d/build-toolchain.sh