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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id 8sm2132159lfq.200.2022.01.30.15.58.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Jan 2022 15:58:02 -0800 (PST) From: Philipp Tomsich To: qemu-devel@nongnu.org Subject: [PATCH v4 0/7] target/riscv: Add XVentanaCondOps and supporting infrastructure changes Date: Mon, 31 Jan 2022 00:57:52 +0100 Message-Id: <20220130235759.1378871-1-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.33.1 MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::135 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::135; envelope-from=philipp.tomsich@vrull.eu; helo=mail-lf1-x135.google.com X-Spam_score_int: -12 X-Spam_score: -1.3 X-Spam_bar: - X-Spam_report: (-1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , Kito Cheng , Alistair Francis , Greg Favor , Philipp Tomsich Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" In adding our first X-extension (i.e., vendor-defined) on RISC-V with XVentanaCondOps, we need to add a few instructure improvements to make it easier to add similar vendor-defined extensions in the future: - refactor access to the cfg->ext_* fields by making a pointer to the cfg structure (as cfg_ptr) available via DisasContext - add a table-based list of decoders to invoke, each being guarded by a guard/predicate-function, that can be used to either add vendor extensions, large extensions or override (by listing the decoder before the one for standard extensions) patterns to handle errata Changes in v4: - use a typedef into 'RISCVCPUConfig' (instead of the explicit 'struct RISCVCPUConfig') to comply with the coding standard (as suggested in Richard's review of v3) - add braces to comply with coding standard (as suggested by Richard) - merge the two if-statements to reduce clutter after (now that the braces have been added) Changes in v3: - (new patch) refactor 'struct RISCVCPUConfig' - (new patch) copy pointer to element cfg into DisasContext - (new patch) test extension-availability through cfg_ptr in DisasContext, removing the fields that have been copied into DisasContext directly - (new patch) change Zb[abcs] implementation to use cfg_ptr (copied into DisasContext) instead of going throuhg RISCV_CPU - expose only the DisasContext* to predicate functions - mark the table of decoder functions as static - drop the inline from always_true_p, until the need arises (i.e., someone finds a use for it and calls it directly) - rewrite to drop the 'handled' temporary in iterating over the decoder table, removing the assignment in the condition of the if - rename to trans_xventanacondops.c.inc (i.e. with the '.c') - (in MATERIALISE_EXT_PREDICATE) don't annotate the predicate function for testing the availability of individual extensions as 'inline' and don't make CPURISCVState* visible to these predicate functions - add a MAINTAINERS entry for XVentanaCondOps Changes in v2: - (new patch) iterate over a table of guarded decoder functions - Split off decode table into XVentanaCondOps.decode - Wire up XVentanaCondOps in the decoder-table Philipp Tomsich (7): target/riscv: refactor (anonymous struct) RISCVCPU.cfg into 'struct RISCVCPUConfig' target/riscv: riscv_tr_init_disas_context: copy pointer-to-cfg into cfg_ptr target/riscv: access configuration through cfg_ptr in DisasContext target/riscv: access cfg structure through DisasContext target/riscv: iterate over a table of decoders target/riscv: Add XVentanaCondOps custom extension target/riscv: add a MAINTAINERS entry for XVentanaCondOps MAINTAINERS | 7 ++ target/riscv/XVentanaCondOps.decode | 25 +++++ target/riscv/cpu.c | 3 + target/riscv/cpu.h | 81 +++++++------- target/riscv/insn_trans/trans_rvb.c.inc | 8 +- target/riscv/insn_trans/trans_rvi.c.inc | 2 +- target/riscv/insn_trans/trans_rvv.c.inc | 104 +++++++++--------- target/riscv/insn_trans/trans_rvzfh.c.inc | 4 +- .../insn_trans/trans_xventanacondops.c.inc | 39 +++++++ target/riscv/meson.build | 1 + target/riscv/translate.c | 60 ++++++---- 11 files changed, 219 insertions(+), 115 deletions(-) create mode 100644 target/riscv/XVentanaCondOps.decode create mode 100644 target/riscv/insn_trans/trans_xventanacondops.c.inc