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[70.228.75.190]) by smtp.gmail.com with ESMTPSA id 1sm1596841oab.16.2022.02.06.01.18.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Feb 2022 01:18:46 -0800 (PST) From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v3 0/6] Privilege version update Date: Sun, 6 Feb 2022 01:18:29 -0800 Message-Id: <20220206091835.1244296-1-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::c31 (failed) Received-SPF: pass client-ip=2607:f8b0:4864:20::c31; envelope-from=atishp@rivosinc.com; helo=mail-oo1-xc31.google.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , Atish Patra , Palmer Dabbelt , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" RISC-V International (RVI) has ratified many RISC-V ISA extensions recently[1]. The privileged specification version is also upgraded to v1.12. It means certain CSRs introduced in v1.12 should only be accessible only if the priv specification version supported is equal or greater than v1.12. Doing this check in predicate function is not scalable as there will be new CSRs introduced in the future versions of the privileged specification. This series tries to address this problem by adding a field in the csr_ops which can be checked in csrrw function before invoking the predicate function. To keep the code churn to minimum, it is assumed that the minimum version of the privilege version supported for any CSR is v1.10 unless specified explicitly in the csr_ops table. Any new CSRs introduced in v1.12 have been updated accordingly. This will work fine for any ratified extensions. However, it is bit unclear what should be done for the stable draft extensions. My suggestion is not to update the priv field in the CSR ops table until the extension is marked experimental (i.e. not frozen/ratified). Once the extension is ratified and graduated from experimental to available stage, the privileged spec version should be updated in the csr table if required. I am open to other suggestions as well. [1] https://wiki.riscv.org/display/TECH/Recently+Ratified+Extensions This series is rebased on top of the AIA v8 to avoid conflicts. Changes from v2->v3: 1. Only update the bits defined in *envcfg CSR Changes from v1->v2: 1. Unified both [m/h]envcfg & [m/h]envcfgh into one. 2. Changed the priv spec version enumeration 3. Improved csr_ops table to provide better redability. 4. Fixed the compilation error for CONFIG_USER_ONLY 5. Rebased on top of the AIA series. Atish Patra (6): target/riscv: Define simpler privileged spec version numbering target/riscv: Add the privileged spec version 1.12.0 target/riscv: Introduce privilege version field in the CSR ops. target/riscv: Add support for mconfigptr target/riscv: Add *envcfg* CSRs support target/riscv: Enable privileged spec version 1.12 target/riscv/cpu.c | 8 +- target/riscv/cpu.h | 15 ++- target/riscv/cpu_bits.h | 40 ++++++++ target/riscv/csr.c | 217 +++++++++++++++++++++++++++++++++------- target/riscv/machine.c | 24 +++++ 5 files changed, 264 insertions(+), 40 deletions(-) --- 2.30.2