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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id a26-20020a19fc1a000000b0044846901ea6sm220845lfi.42.2022.03.16.09.46.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Mar 2022 09:46:46 -0700 (PDT) From: "Edgar E. Iglesias" To: qemu-devel@nongnu.org Subject: [PATCH v3 0/6] hw/arm: zynqmp: Add CRF and APU control to support PSCI Date: Wed, 16 Mar 2022 17:46:39 +0100 Message-Id: <20220316164645.2303510-1-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::133 (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::133; envelope-from=edgar.iglesias@gmail.com; helo=mail-lf1-x133.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@xilinx.com, peter.maydell@linaro.org, luc@lmichel.fr, edgar.iglesias@amd.com, sai.pavan.boddu@xilinx.com, frasse.iglesias@gmail.com, alistair@alistair23.me, richard.henderson@linaro.org, f4bug@amsat.org, francisco.iglesias@xilinx.com, frederic.konrad@adacore.com, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: "Edgar E. Iglesias" This adds the necessary modeling to support some of our firmware tests at EL3 implementing PSCI (TBM). These are the test-cases that were previously relying on QEMU's builtin PSCI emulation. Cheers, Edgar ChangeLog: v2 -> v3: * Make RVBAR_ELx register reflect updated rvbar * Sample rvbar prop at reset * Remove setting of minimum_version_id_old * Use OBJECT_DECLARE_SIMPLE_TYPE v1 -> v2: * crf: Change APU_MAX_CPU to CRF_MAX_CPU * crf: Remove empty interfaces * crf: Add include guards * apu-ctrl: Change NUM_CPUS to APU_MAX_CPU * apu-ctrl: Fix indentation * apu-ctrl: Remove empty interfaces * apu-ctrl: Add include guards * xlnx-zynqmp: Add comment clarifying SER/DESerializer Edgar E. Iglesias (6): hw/arm/xlnx-zynqmp: Add an unimplemented SERDES area target/arm: Make rvbar settable after realize hw/misc: Add a model of the Xilinx ZynqMP CRF hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF hw/misc: Add a model of the Xilinx ZynqMP APU Control hw/arm/xlnx-zynqmp: Connect the ZynqMP APU Control include/hw/arm/xlnx-zynqmp.h | 4 + include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 93 +++++++++ include/hw/misc/xlnx-zynqmp-crf.h | 211 ++++++++++++++++++++ target/arm/cpu.h | 3 +- hw/arm/xlnx-zynqmp.c | 46 ++++- hw/misc/xlnx-zynqmp-apu-ctrl.c | 253 +++++++++++++++++++++++ hw/misc/xlnx-zynqmp-crf.c | 266 +++++++++++++++++++++++++ target/arm/cpu.c | 12 +- target/arm/helper.c | 10 +- hw/misc/meson.build | 2 + 10 files changed, 889 insertions(+), 11 deletions(-) create mode 100644 include/hw/misc/xlnx-zynqmp-apu-ctrl.h create mode 100644 include/hw/misc/xlnx-zynqmp-crf.h create mode 100644 hw/misc/xlnx-zynqmp-apu-ctrl.c create mode 100644 hw/misc/xlnx-zynqmp-crf.c