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[00/10] VDIV/VMOD Implementation

Message ID 20220330202515.66554-1-lucas.araujo@eldorado.org.br (mailing list archive)
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Series VDIV/VMOD Implementation | expand

Message

Lucas Mateus Martins Araujo e Castro March 30, 2022, 8:25 p.m. UTC 
From: "Lucas Mateus Castro (alqotel)" <lucas.araujo@eldorado.org.br>

This patch series is an implementation of the vector divide, vector
divide extended and vector modulo instructions from PowerISA 3.1

The first 2 patches are Matheus' patches used here since the divs256 and
divu256 functions use int128_lshift and int128_urshift.

Lucas Mateus Castro (alqotel) (8):
  target/ppc: Implemented vector divide instructions
  target/ppc: Implemented vector divide quadword
  target/ppc: Implemented vector divide extended word
  Implemented unsigned 256-by-128 division
  Implemented signed 256-by-128 division
  target/ppc: Implemented remaining vector divide extended
  target/ppc: Implemented vector module word/doubleword
  target/ppc: Implemented vector module quadword

Matheus Ferst (2):
  qemu/int128: avoid undefined behavior in int128_lshift
  qemu/int128: add int128_urshift

 include/qemu/host-utils.h           |  16 +++
 include/qemu/int128.h               |  53 +++++++-
 target/ppc/helper.h                 |   8 ++
 target/ppc/insn32.decode            |  23 ++++
 target/ppc/int_helper.c             | 109 +++++++++++++++++
 target/ppc/translate/vmx-impl.c.inc | 148 +++++++++++++++++++++++
 tests/unit/test-int128.c            |  32 +++++
 util/host-utils.c                   | 179 ++++++++++++++++++++++++++++
 8 files changed, 566 insertions(+), 2 deletions(-)