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Fri, 8 Apr 2022 13:13:03 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8CA5EA405B; Fri, 8 Apr 2022 13:13:03 +0000 (GMT) Received: from localhost.localdomain.com (unknown [9.145.145.202]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 8 Apr 2022 13:13:03 +0000 (GMT) From: Frederic Barrat To: clg@kaod.org, danielhb413@gmail.com, mst@redhat.com, marcel.apfelbaum@gmail.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 0/2] Remove PCIE root bridge LSI on powernv Date: Fri, 8 Apr 2022 15:13:01 +0200 Message-Id: <20220408131303.147840-1-fbarrat@linux.ibm.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: IjibuNaBe3N3hwD1zvNXYymQfzpuoA7q X-Proofpoint-ORIG-GUID: 5wv0OH9foLbiWNuFhEgveeNDfUmErpHH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-04-08_04,2022-04-08_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 adultscore=0 mlxlogscore=812 bulkscore=0 lowpriorityscore=0 impostorscore=0 phishscore=0 malwarescore=0 clxscore=1015 mlxscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2204080067 Received-SPF: pass client-ip=148.163.158.5; envelope-from=fbarrat@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The powernv8/powernv9/powernv10 machines allocate a LSI for their root port bridge, which is not the case on real hardware. The default root port implementation in qemu requests a LSI. Since the powernv implementation derives from it, that's where the LSI is coming from. This series fixes it, so that the model matches the hardware. However, the code in hw/pci to handle AER and hotplug events assume a LSI is defined. It tends to assert/deassert a LSI if MSI or MSIX is not enabled. Since we have hardware where that is not true, this patch also fixes a few code paths to check if a LSI is configured before trying to trigger it. Changes from v1: - addressed comments from Daniel Frederic Barrat (2): pcie: Don't try triggering a LSI when not defined ppc/pnv: Remove LSI on the PCIE host bridge hw/pci-host/pnv_phb3.c | 1 + hw/pci-host/pnv_phb4.c | 1 + hw/pci/pcie.c | 5 +++-- hw/pci/pcie_aer.c | 2 +- 4 files changed, 6 insertions(+), 3 deletions(-)