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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id fv7-20020a17090b0e8700b001ce18c551dcsm14963381pjb.19.2022.04.19.02.08.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Apr 2022 02:08:52 -0700 (PDT) From: frank.chang@sifive.com To: qemu-devel@nongnu.org Subject: [PATCH v3 0/4] Support ACLINT 32/64-bit mtimecmp/mtime read/write accesses Date: Tue, 19 Apr 2022 17:08:41 +0800 Message-Id: <20220419090848.9018-1-frank.chang@sifive.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=frank.chang@sifive.com; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Frank Chang , qemu-riscv@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Frank Chang This patchset makes ACLINT mtime to be writable as RISC-V privilege spec defines that mtime is exposed as a memory-mapped machine-mode read-write register. Also, mtimecmp and mtime should be 32/64-bit memory accessible registers. ACLINT reset function is also added, which requires mtime to be resetable if we need to support core power-gating feature in the future. This patchset is the updated verion of: https://patchew.org/QEMU/20220126095448.2964-1-frank.chang@sifive.com/ Changelog: v3: * Forbid 8-byte write access to timecmp_hi and time_hi. * Add ACLINT reset function. v2: * Support 32/64-bit mtimecmp/mtime memory accesses. * Add .impl.[min|max]_access_size declaration. Frank Chang (3): hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINT hw/intc: Make RISC-V ACLINT mtime MMIO register writable Jim Shu (1): hw/intc: riscv_aclint: Add reset function of ACLINT devices hw/intc/riscv_aclint.c | 144 ++++++++++++++++++++++++++------- include/hw/intc/riscv_aclint.h | 1 + target/riscv/cpu.h | 8 +- target/riscv/cpu_helper.c | 4 +- 4 files changed, 121 insertions(+), 36 deletions(-) --- 2.35.1