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([122.167.97.237]) by smtp.gmail.com with ESMTPSA id l22-20020a17090a071600b001d9781de67fsm8195568pjl.31.2022.04.28.20.34.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Apr 2022 20:34:36 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Subject: [PATCH 0/4] QEMU RISC-V nested virtualization fixes Date: Fri, 29 Apr 2022 09:04:05 +0530 Message-Id: <20220429033409.258707-1-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=apatel@ventanamicro.com; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Anup Patel , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Atish Patra Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This series does fixes and improvements to have nested virtualization on QEMU RISC-V. The first two patches are fixes whereas the second two patches make nested virtualization performance better on for QEMU RISC-V. These patches can also be found in riscv_nested_fixes_v1 branch at: https://github.com/avpatel/qemu.git The RISC-V nested virtualization was tested on QEMU RISC-V using Xvisor RISC-V which has required hypervisor support to run another hypervisor as Guest/VM. Anup Patel (4): target/riscv: Fix csr number based privilege checking target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode target/riscv: Set [m|s]tval for both illegal and virtual instruction traps target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() target/riscv/cpu.c | 2 + target/riscv/cpu.h | 8 +- target/riscv/cpu_helper.c | 170 ++++++++++++++++++++++++++++++++++++-- target/riscv/csr.c | 8 +- target/riscv/instmap.h | 41 +++++++++ target/riscv/translate.c | 17 +++- 6 files changed, 234 insertions(+), 12 deletions(-)