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([171.76.113.90]) by smtp.gmail.com with ESMTPSA id x2-20020a170902820200b0015eafc485c8sm1958726pln.289.2022.05.11.07.46.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 07:46:22 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Subject: [PATCH v2 0/8] QEMU RISC-V nested virtualization fixes Date: Wed, 11 May 2022 20:15:20 +0530 Message-Id: <20220511144528.393530-1-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=apatel@ventanamicro.com; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This series does fixes and improvements to have nested virtualization on QEMU RISC-V. These patches can also be found in riscv_nested_fixes_v2 branch at: https://github.com/avpatel/qemu.git The RISC-V nested virtualization was tested on QEMU RISC-V using Xvisor RISC-V which has required hypervisor support to run another hypervisor as Guest/VM. Changes since v1: - Set write_gva to env->two_stage_lookup which ensures that for HS-mode to HS-mode trap write_gva is true only for HLV/HSV instructions - Included "[PATCH 0/3] QEMU RISC-V priv spec version fixes" patches in this series for easy review - Re-worked PATCH7 to force disable extensions if required priv spec version is not staisfied - Added new PATCH8 to fix "aia=aplic-imsic" mode of virt machine Anup Patel (8): target/riscv: Fix csr number based privilege checking target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode target/riscv: Set [m|s]tval for both illegal and virtual instruction traps target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() target/riscv: Don't force update priv spec version to latest target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher target/riscv: Force disable extensions if priv spec version does not match hw/riscv: virt: Fix interrupt parent for dynamic platform devices hw/riscv/virt.c | 25 +++--- target/riscv/cpu.c | 46 +++++++++- target/riscv/cpu.h | 8 +- target/riscv/cpu_bits.h | 3 + target/riscv/cpu_helper.c | 172 ++++++++++++++++++++++++++++++++++++-- target/riscv/csr.c | 10 ++- target/riscv/instmap.h | 41 +++++++++ target/riscv/translate.c | 17 +++- 8 files changed, 292 insertions(+), 30 deletions(-)