From patchwork Wed May 11 21:59:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Atish Kumar Patra X-Patchwork-Id: 12846652 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9120EC433EF for ; Wed, 11 May 2022 22:02:25 +0000 (UTC) Received: from localhost ([::1]:49328 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nouPY-0007CS-C3 for qemu-devel@archiver.kernel.org; Wed, 11 May 2022 18:02:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47840) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nouNM-0004ST-7x for qemu-devel@nongnu.org; Wed, 11 May 2022 18:00:08 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]:34693) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nouNI-0006a9-N3 for qemu-devel@nongnu.org; Wed, 11 May 2022 18:00:07 -0400 Received: by mail-pg1-x533.google.com with SMTP id g184so2939733pgc.1 for ; Wed, 11 May 2022 15:00:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=94lHMb0SMUV/d3HDhgbWVkMvpr3odVJ5B57hrgu0tRQ=; b=JbCwixfe+H4+ZwWUd9LLzeelvpiLX7vsd6ha4dr0l3gtuzy21oFuqVSkKX5te98U06 pnhpdw7HQz3gv+DHBPrMxcLRZ60St/11kKlLDJC6+iRskcRNPaNEtD8I3cxvDefQci2r iUV4v6hM4zn3o2ozt7CPJ0kP3XvzujwgjHfVg/hbwvBJtIwQ+QjAlN2LPxnN9x8afIBO XzijS73Cc5Asv/Y25rdeiwfGbUjqQLwlwm5I90Jf+SRVmpxol8Igubkp7aOvxW8WtMes 7WUYCFaQgT2QPweRb5nrVxKVCOHbvPcYUmpGyzndOYAaVbQLfVvLiPlqEdkhdqALhFUz fsqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=94lHMb0SMUV/d3HDhgbWVkMvpr3odVJ5B57hrgu0tRQ=; b=XGW4gMzP5st0e/w/qyo6ED12gytkXHZukikrgnkIS3dm2Hvcer7kPfzP5K4coXMREe Pdovl2z88En2KGcE8Z8VHT1MS1W4N4IV9hbM6jiA5MNm//IdLcq6FyujaL/ajvHK6dHZ FD2TNfqbCKmkzawczz1YAuthR+mIHqMg4O1lhZmurQNl6zwmIu3o6jKBVX8Ow9bjVMw0 ZrBlx9NORSFZhpBqH3iqurdsqt443w3Tut/rZdoHAX+MCDtC3ciF+sH67Tp/tIozYNGM +nbUgirRWXSzQfehPrnATkaDLAeqlHw1hXsuKFCiK5nzZxb8uvggFmoC7Lh5X2HnpGip 1eLQ== X-Gm-Message-State: AOAM530Z1Sm8Vb7OQcAuOOQmdfo731eufZP9fudQPK0h7S1Ppcb/ibcW 6Pwofqn2GX1ms2Vlkc6vqoNV9Q== X-Google-Smtp-Source: ABdhPJzyBnGMP9PX2cBFzygv2mNgslBCn9n2H4Iyd9f2cm+ouYYkHO1c8kOpYmxgSR4bp9+96nRLXA== X-Received: by 2002:a63:5917:0:b0:39c:c450:3143 with SMTP id n23-20020a635917000000b0039cc4503143mr22306736pgb.531.1652306402696; Wed, 11 May 2022 15:00:02 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id r23-20020a62e417000000b0050dc762816asm2261303pfh.68.2022.05.11.15.00.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 15:00:02 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Alistair Francis , Bin Meng , Palmer Dabbelt , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v8 00/12] Improve PMU support Date: Wed, 11 May 2022 14:59:44 -0700 Message-Id: <20220511215956.2351243-1-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=atishp@rivosinc.com; helo=mail-pg1-x533.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The latest version of the SBI specification includes a Performance Monitoring Unit(PMU) extension[1] which allows the supervisor to start/stop/configure various PMU events. The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions, and 'cofpmf' for Count OverFlow and Privilege Mode Filtering) extension[2] allows the perf like tool to handle overflow interrupts and filtering support. This series implements full PMU infrastructure to support PMU in virt machine. This will allow us to add any PMU events in future. Currently, this series enables the following omu events. 1. cycle count 2. instruction count 3. DTLB load/store miss 4. ITLB prefetch miss The first two are computed using host ticks while last three are counted during cpu_tlb_fill. We can do both sampling and count from guest userspace. This series has been tested on both RV64 and RV32. Both Linux[3] and Opensbi[4] patches are required to get the perf working. Here is an output of perf stat/report while running hackbench with latest OpenSBI & Linux kernel. Perf stat: ========== [root@fedora-riscv ~]# perf stat -e cycles -e instructions -e dTLB-load-misses -e dTLB-store-misses -e iTLB-load-misses \ > perf bench sched messaging -g 1 -l 10 # Running 'sched/messaging' benchmark: # 20 sender and receiver processes per group # 1 groups == 40 processes run Total time: 0.265 [sec] Performance counter stats for 'perf bench sched messaging -g 1 -l 10': 4,167,825,362 cycles 4,166,609,256 instructions # 1.00 insn per cycle 3,092,026 dTLB-load-misses 258,280 dTLB-store-misses 2,068,966 iTLB-load-misses 0.585791767 seconds time elapsed 0.373802000 seconds user 1.042359000 seconds sys Perf record: ============ [root@fedora-riscv ~]# perf record -e cycles -e instructions \ > -e dTLB-load-misses -e dTLB-store-misses -e iTLB-load-misses -c 10000 \ > perf bench sched messaging -g 1 -l 10 # Running 'sched/messaging' benchmark: # 20 sender and receiver processes per group # 1 groups == 40 processes run Total time: 1.397 [sec] [ perf record: Woken up 10 times to write data ] Check IO/CPU overload! [ perf record: Captured and wrote 8.211 MB perf.data (214486 samples) ] [root@fedora-riscv riscv]# perf report Available samples 107K cycles ◆ 107K instructions ▒ 250 dTLB-load-misses ▒ 13 dTLB-store-misses ▒ 172 iTLB-load-misses .. Changes from v7->v8: 1. Removeding ordering constraints for mhpmcounter & mhpmevent. Changes from v6->v7: 1. Fixed all the compilation errors for the usermode. Changes from v5->v6: 1. Fixed compilation issue with PATCH 1. 2. Addressed other comments. Changes from v4->v5: 1. Rebased on top of the -next with following patches. - isa extension - priv 1.12 spec 2. Addressed all the comments on v4 3. Removed additional isa-ext DT node in favor of riscv,isa string update Changes from v3->v4: 1. Removed the dummy events from pmu DT node. 2. Fixed pmu_avail_counters mask generation. 3. Added a patch to simplify the predicate function for counters. Changes from v2->v3: 1. Addressed all the comments on PATCH1-4. 2. Split patch1 into two separate patches. 3. Added explicit comments to explain the event types in DT node. 4. Rebased on latest Qemu. Changes from v1->v2: 1. Dropped the ACks from v1 as signficant changes happened after v1. 2. sscofpmf support. 3. A generic counter management framework. [1] https://github.com/riscv-non-isa/riscv-sbi-doc/blob/master/riscv-sbi.adoc [2] https://drive.google.com/file/d/171j4jFjIkKdj5LWcExphq4xG_2sihbfd/edit [3] https://github.com/atishp04/qemu/tree/riscv_pmu_v8 Atish Patra (12): target/riscv: Fix PMU CSR predicate function target/riscv: Implement PMU CSR predicate function for S-mode target/riscv: pmu: Rename the counters extension to pmu target/riscv: pmu: Make number of counters configurable target/riscv: Implement mcountinhibit CSR target/riscv: Add support for hpmcounters/hpmevents target/riscv: Support mcycle/minstret write operation target/riscv: Add sscofpmf extension support target/riscv: Simplify counter predicate function target/riscv: Add few cache related PMU events hw/riscv: virt: Add PMU DT node to the device tree target/riscv: Update the privilege field for sscofpmf CSRs hw/riscv/virt.c | 28 ++ target/riscv/cpu.c | 14 +- target/riscv/cpu.h | 56 ++- target/riscv/cpu_bits.h | 59 +++ target/riscv/cpu_helper.c | 25 ++ target/riscv/csr.c | 903 ++++++++++++++++++++++++++++---------- target/riscv/machine.c | 25 ++ target/riscv/meson.build | 3 +- target/riscv/pmu.c | 432 ++++++++++++++++++ target/riscv/pmu.h | 36 ++ 10 files changed, 1346 insertions(+), 235 deletions(-) create mode 100644 target/riscv/pmu.c create mode 100644 target/riscv/pmu.h --- 2.25.1