From patchwork Wed May 25 05:34:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jamin Lin X-Patchwork-Id: 12860710 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A3AAFC433EF for ; Wed, 25 May 2022 05:57:59 +0000 (UTC) Received: from localhost ([::1]:58238 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ntk1u-0008K8-Fm for qemu-devel@archiver.kernel.org; Wed, 25 May 2022 01:57:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50390) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ntjgT-0001AE-Sf; Wed, 25 May 2022 01:35:49 -0400 Received: from twspam01.aspeedtech.com ([211.20.114.71]:52379) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ntjgR-0003xq-Nl; Wed, 25 May 2022 01:35:49 -0400 Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 24P5Kg9i022843; Wed, 25 May 2022 13:20:42 +0800 (GMT-8) (envelope-from jamin_lin@aspeedtech.com) Received: from localhost.localdomain (192.168.70.123) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 25 May 2022 13:34:47 +0800 From: Jamin Lin To: =?utf-8?q?C=C3=A9dric_Le_Goater?= , Peter Maydell , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" CC: , , Subject: [PATCH v2 0/4] hw/gpio Add ASPEED GPIO model for AST1030 Date: Wed, 25 May 2022 13:34:40 +0800 Message-ID: <20220525053444.27228-1-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 X-Originating-IP: [192.168.70.123] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 24P5Kg9i022843 Received-SPF: pass client-ip=211.20.114.71; envelope-from=jamin_lin@aspeedtech.com; helo=twspam01.aspeedtech.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" -v2 changes Create separate patches to support the following features 1. Add GPIO read/write trace event. 2. Support GPIO index mode for write operation. It did not support GPIO index mode for read operation. 3. AST1030 integrates one set of Parallel GPIO Controller with maximum 151 control pins, which are 21 groups (A~U, exclude pin: M6 M7 Q5 Q6 Q7 R0 R1 R4 R5 R6 R7 S0 S3 S4 S5 S6 S7 ) and the group T and U are input only. 4. replace HWADDR_PRIx with PRIx64 Jamin Lin (4): hw/gpio Add GPIO read/write trace event. hw/gpio: Add ASPEED GPIO model for AST1030 hw/gpio support GPIO index mode for write operation. hw/gpio: replace HWADDR_PRIx with PRIx64 hw/arm/aspeed_ast10x0.c | 11 ++ hw/gpio/aspeed_gpio.c | 257 +++++++++++++++++++++++++++++++--- hw/gpio/trace-events | 5 + include/hw/gpio/aspeed_gpio.h | 16 ++- 4 files changed, 269 insertions(+), 20 deletions(-)