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([171.76.87.82]) by smtp.gmail.com with ESMTPSA id x53-20020a056a000bf500b00517c84fd24asm389019pfu.172.2022.06.15.20.16.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jun 2022 20:16:43 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Subject: [PATCH 0/2] AIA draft v0.3.0 support for QEMU RISC-V Date: Thu, 16 Jun 2022 08:45:41 +0530 Message-Id: <20220616031543.953776-1-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=apatel@ventanamicro.com; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The latest AIA draft v0.3.0 addresses comments from the architecture review committee. (Refer, https://github.com/riscv/riscv-aia/releases/tag/0.3.0-draft.31) There are primarily two changes: 1) Removing various [m|s|vs]seteienum, [m|s|vs]clreienum, [m|s|vs]seteipnum, and [m|s|vs]clrei;num CSRs because these CSRs were mostly for software convienence. 2) Simplifying the default priority assignment for local interrupts These patches can also be found in riscv_aia_update_v1 branch at: https://github.com/avpatel/qemu.git Corresponding changes in OpenSBI and Linux were small and these can be found at: riscv_aia_update_v1 branch of https://github.com/avpatel/opensbi.git riscv_aia_v1 branch of https://github.com/avpatel/linux.git Anup Patel (2): target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits target/riscv: Update default priority table for local interrupts target/riscv/cpu_bits.h | 26 +------ target/riscv/cpu_helper.c | 134 +++++++++++++++++----------------- target/riscv/csr.c | 150 +------------------------------------- 3 files changed, 72 insertions(+), 238 deletions(-)