From patchwork Mon Aug 8 08:58:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaoyao Li X-Patchwork-Id: 12938596 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 16D87C00140 for ; Mon, 8 Aug 2022 09:12:20 +0000 (UTC) Received: from localhost ([::1]:34010 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oKyo7-0005y3-53 for qemu-devel@archiver.kernel.org; Mon, 08 Aug 2022 05:12:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56774) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oKyax-0005Io-Bu for qemu-devel@nongnu.org; Mon, 08 Aug 2022 04:58:45 -0400 Received: from mga09.intel.com ([134.134.136.24]:15910) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oKyau-0001oF-Or for qemu-devel@nongnu.org; Mon, 08 Aug 2022 04:58:43 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1659949120; x=1691485120; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=pvMgcmAhjFBY6Z506Vgh8jh6X3m82T4afmcR2kHV3X8=; b=J3dvoxqfI2S+edb45QjawO7LnP8GmF7svZVfb6VaWY2mDBx0mLbx8Y9/ KPfeH04oJA4nQ6L764ljEqxddfEBFGzfZFccOQmo2LoqIYNrJlQfJxGE1 4W3wcQ+nDc1ktvBvwXX+pYAdUOxsgbwP7ylwaluxT+hDrFrzDQA5PfA4C 7ZmzGK6Javk5g//7qBT1Urp5mGjTmod4rBVBxaJ4Ia/TOSrArbqpZy4Ew EcJpdyeoN6IWpiFhF/UeET5LCakXzRQ7X4YIK4BSVWz8ilxpqTkygpn+U Pomg6jcyeOQm1M7aQACYdHR/ZGUcUJEXv0hiocMpcvbaG3t3E451+cui7 g==; X-IronPort-AV: E=McAfee;i="6400,9594,10432"; a="291319223" X-IronPort-AV: E=Sophos;i="5.93,221,1654585200"; d="scan'208";a="291319223" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Aug 2022 01:58:36 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.93,221,1654585200"; d="scan'208";a="931970528" Received: from lxy-dell.sh.intel.com ([10.239.48.38]) by fmsmga005.fm.intel.com with ESMTP; 08 Aug 2022 01:58:34 -0700 From: Xiaoyao Li To: Paolo Bonzini , Marcelo Tosatti Cc: qemu-devel@nongnu.org, kvm@vger.kernel.org Subject: [PATCH v2 0/8] Make Intel PT configurable Date: Mon, 8 Aug 2022 16:58:26 +0800 Message-Id: <20220808085834.3227541-1-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 Received-SPF: pass client-ip=134.134.136.24; envelope-from=xiaoyao.li@intel.com; helo=mga09.intel.com X-Spam_score_int: -24 X-Spam_score: -2.5 X-Spam_bar: -- X-Spam_report: (-2.5 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, HK_RANDOM_ENVFROM=0.998, HK_RANDOM_FROM=0.998, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Initial virtualization of Intel PT was added by making it as fixed feature set of ICX's capabilities. However, it breaks the Intel PT exposure on SPR machine because SPR has less PT capabilities of CPUID(0x14,1):EBX[15:0]. This series aims to make Intel PT configurable that named CPU model can define its own PT feature set and "-cpu host/max" can use host pass-through feature set of Intel PT. At the same time, it also ensures existing named CPU model to generate the same PT CPUID set as before to not break live migration. Changes in v2: - split out 3 patches (per Eduardo's comment) - determine if the named cpu model uses default Intel PT capabilities (to be compatible with the old behavior) by condition that all PT feature leaves are all zero. v1: https://lore.kernel.org/qemu-devel/20210909144150.1728418-1-xiaoyao.li@intel.com/ Xiaoyao Li (8): target/i386: Print CPUID subleaf info for unsupported feature target/i386/intel-pt: Fix INTEL_PT_ADDR_RANGES_NUM_MASK target/i386/intel-pt: Introduce FeatureWordInfo for Intel PT CPUID leaf 0xD target/i386/intel-pt: print special message for INTEL_PT_ADDR_RANGES_NUM target/i386/intel-pt: Rework/rename the default INTEL-PT feature set target/i386/intel-pt: Enable host pass through of Intel PT target/i386/intel-pt: Define specific PT feature set for IceLake-server and Snowridge target/i386/intel-pt: Access MSR_IA32_RTIT_ADDRn based on guest CPUID configuration target/i386/cpu.c | 291 +++++++++++++++++++++++++++++++----------- target/i386/cpu.h | 40 +++++- target/i386/kvm/kvm.c | 8 +- 3 files changed, 261 insertions(+), 78 deletions(-)