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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id d21-20020a170906305500b0073d6ab5bcaasm6479034ejd.212.2022.09.06.05.22.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 05:22:46 -0700 (PDT) From: Christoph Muellner To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Alistair Francis , Bin Meng , Philipp Tomsich , =?utf-8?q?Heiko_St=C3=BCbner?= , Palmer Dabbelt , Richard Henderson , Nelson Chu , Kito Cheng , Cooper Qu , Lifang Xia , Yunhai Shang , Zhiwei Liu Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH 00/11] Add support for the T-Head vendor extensions Date: Tue, 6 Sep 2022 14:22:32 +0200 Message-Id: <20220906122243.1243354-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.37.2 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::533; envelope-from=christoph.muellner@vrull.eu; helo=mail-ed1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" From: Christoph Müllner This series introduces support for the T-Head vendor extensions, which are implemented e.g. in the XuanTie C906 and XuanTie C910 processors: * XTheadBa * XTheadBb * XTheadBs * XTheadCmo * XTheadCondMov * XTheadFMemIdx * XTheadMac * XTheadMemIdx * XTheadMemPair * XTheadSync The xthead* extensions are documented here: https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.0.0/xthead-2022-09-05-2.0.0.pdf The "th." instruction prefix prevents future conflicts with standard extensions and has been documentented in a PR for the RISC-V toolchain conventions: https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19 The goal of this patchset is to provide access to these instruction so that compilers/users can optimize SW accordingly. Note, that the T-Head vendor extensions do not contain all vendor-specific functionality of the T-Head SoCs (e.g. no vendor-specific CSRs are included). Instead the extensions cover coherent functionality, that is exposed to S and U mode. To enable the extensions above, the following two methods are possible: * add the extension to the arch string (e.g. * QEMU_CPU="any,xtheadcmo=true,xtheadsync=true") * implicitly select the extensions via CPU selection (e.g. * QEMU_CPU="thead-c910") This patchset attempts to minimize code changes in generic/infrastructure code. This patchset allows to boot the Xuantie Linux kernel. Christoph Müllner (11): riscv: Add privilege level to DisasContext RISC-V: Adding T-Head CMO instructions RISC-V: Adding T-Head SYNC instructions RISC-V: Adding T-Head Bitmanip instructions RISC-V: Adding T-Head CondMov instructions RISC-V: Adding T-Head multiply-accumulate instructions RISC-V: Adding T-Head XMAE support RISC-V: Adding T-Head MemPair extension RISC-V: Adding T-Head MemIdx extension RISC-V: Adding T-Head FMemIdx extension RISC-V: Add initial support for T-Head C906 and C910 CPUs target/riscv/cpu.c | 43 + target/riscv/cpu.h | 14 + target/riscv/cpu_helper.c | 6 +- target/riscv/cpu_vendorid.h | 6 + target/riscv/insn_trans/trans_xthead.c.inc | 874 +++++++++++++++++++++ target/riscv/meson.build | 10 + target/riscv/translate.c | 42 +- target/riscv/xtheadba.decode | 46 ++ target/riscv/xtheadbb.decode | 62 ++ target/riscv/xtheadbs.decode | 32 + target/riscv/xtheadcmo.decode | 43 + target/riscv/xtheadcondmov.decode | 33 + target/riscv/xtheadfmemidx.decode | 34 + target/riscv/xtheadmac.decode | 30 + target/riscv/xtheadmemidx.decode | 73 ++ target/riscv/xtheadmempair.decode | 29 + target/riscv/xtheadsync.decode | 25 + 17 files changed, 1397 insertions(+), 5 deletions(-) create mode 100644 target/riscv/cpu_vendorid.h create mode 100644 target/riscv/insn_trans/trans_xthead.c.inc create mode 100644 target/riscv/xtheadba.decode create mode 100644 target/riscv/xtheadbb.decode create mode 100644 target/riscv/xtheadbs.decode create mode 100644 target/riscv/xtheadcmo.decode create mode 100644 target/riscv/xtheadcondmov.decode create mode 100644 target/riscv/xtheadfmemidx.decode create mode 100644 target/riscv/xtheadmac.decode create mode 100644 target/riscv/xtheadmemidx.decode create mode 100644 target/riscv/xtheadmempair.decode create mode 100644 target/riscv/xtheadsync.decode