[0/2] ast2600: Disable NEON and VFPv4-D32

Message

Cédric Le Goater Sept. 28, 2022, 4:47 p.m. UTC

Hello,

Currently, the CPU features exposed to the AST2600 QEMU machines are :

  half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt
  vfpd32 lpae evtstrm

But, the features of the Cortex A7 CPU on the Aspeed AST2600 A3 SoC
are :

  half thumb fastmult vfp edsp vfpv3 vfpv3d16 tls vfpv4 idiva idivt
  lpae evtstrm

NEON support should be dropped and, in that case, QEMU should
advertise a VFPv4 unit with 16 double-precision registers, and not 32
registers.

This problem was raised by a buildroot rootfs compiled with vfpv4.
Boot went fine under QEMU but on real HW, user space binaries had
issues with output. Compiling buildroot with vfpv4d16 fixed it and
I didn't dig further. Nevertheless, it would be nice to catch such
issues with QEMU.

Thanks,

C. 

Cédric Le Goater (2):
  target/arm: Disable VFPv4-D32 when NEON is not available
  ast2600: Drop NEON from the CPU features

 hw/arm/aspeed_ast2600.c | 2 ++
 target/arm/cpu.c        | 4 ++++
 2 files changed, 6 insertions(+)

Comments

Richard Henderson Sept. 28, 2022, 5:21 p.m. UTC | #1

On 9/28/22 09:47, Cédric Le Goater wrote:
> As the Cortex A7 MPCore Technical reference says :
> 
>    "When FPU option is selected without NEON, the FPU is VFPv4-D16 and
>    uses 16 double-precision registers. When the FPU is implemented with
>    NEON, the FPU is VFPv4-D32 and uses 32 double-precision registers.
>    This register bank is shared with NEON."
> 
> Modify the mvfr0 register value of the cortex A7 to advertise only 16
> registers when NEON is not available, and not 32 registers.

Looks like A5 has the same language, while A15 says that NEON cannot be enabled without 
VFP (which is the same as all aarch64 cores).  I guess this is a decent compromise.

Reviewed-by: Richard Henderson <[e-mail]>


r~