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[RFC,0/3] Fix some TCG RISC-V backend bugs

Message ID 20221020104154.4276-1-zhiwei_liu@linux.alibaba.com (mailing list archive)
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Series Fix some TCG RISC-V backend bugs | expand

Message

LIU Zhiwei Oct. 20, 2022, 10:41 a.m. UTC 
This patch set fix some bugs in RISC-V backend. It includes:
1. guest regiser using bug in tcg_out_qemu_ld and tcg_out_qemu_st
2. immediate range bug in tcg_out_opc_imm
3. a wrong optimization in tcg_out_addsub2

After this patch set, I can run the 400.perlbench case(spec2006-simple). Besides,
it seems that we can also run RISU on qemu-aarch64(risc-v) now.

I try to run RISU on qemu-aarch64(x86) and qemu-aarch64(risc-v). But this caused
an segment fault. And it's confusing that RISU running on two qemu-aarch64(x86-64)
also caused a segment fault.

LIU Zhiwei (3):
  tcg/riscv: Fix base regsiter for qemu_ld/st
  tcg/riscv: Fix tcg_out_opc_imm when imm exceeds
  tcg/riscv: Remove a wrong optimization for addsub2

 tcg/riscv/tcg-target.c.inc | 35 +++++++++++++++++++++++++++--------
 1 file changed, 27 insertions(+), 8 deletions(-)