From patchwork Sat Oct 22 15:04:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13016426 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 72FB1C3A59D for ; Sun, 23 Oct 2022 20:13:56 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1omgf6-0001LY-L6 for qemu-devel@archiver.kernel.org; Sun, 23 Oct 2022 15:29:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1omG4P-0006zI-QE; Sat, 22 Oct 2022 11:05:56 -0400 Received: from mail-ed1-x52b.google.com ([2a00:1450:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1omG4N-0001zz-NO; Sat, 22 Oct 2022 11:05:53 -0400 Received: by mail-ed1-x52b.google.com with SMTP id b12so16116762edd.6; Sat, 22 Oct 2022 08:05:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=NovAA0yfq1xh3UCa3bxcXd6xqSkYuOKAweWUuQI6MZE=; b=O/Dd6fT6CsxsNDu+7nDfc+JFm8MRrG+0VBmLGbD0M9rKxQ4YbId8HgljMA/wWpGUqG 7wkcKYEv4nQVSIsHAtkmQGKCEr5oGgtN3Rx8bB6U79XwW2Y/EDh3W5VHUrmnxdGbnR+4 gd43v1tRtHp6uYJE0iolUmEX+2d2myNejC2aOMimv3L1zOQOgt3RN0gwgFH6l57nTJA2 m0CmVX3s+qBwJCDBFEu7dyG/NhoLsZ/pYeoTVfSQFm1OrjvvMyylcohRWiK6OKtXoLry icBJoVwR+5GZfgMU1y/jvDKxSwV69mo4p24Yxt8cDXOLK3NHZ6Q8/qkjUw2J0OHlp1ad 6RRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=NovAA0yfq1xh3UCa3bxcXd6xqSkYuOKAweWUuQI6MZE=; b=F5tYh0gfJk/grmjffkKVK44ICz3I7vHU2oU1qXHnqyCfXxE0yZx78F4m1gog5cvAoD HdjARegfADrXkesIgldm8vsLja3GZZy7CrC6ZxzeILPhMhcHMY0yJLILNIysW2fBlduO IoSh/Xi2FPuagykPEWkxLBVoufhJkP1xdK7lT0+Woy+w1lnS2g0433lbUC1tRLS1u0nJ /Khb/4MzUTvFJSLbK7WNqga8EQrd5S+79UTVEqzaJSeFUB+JR6JoM9rbv0Vful0Rg7px DssRDF84dFnRJlCCltfHDgEGK/1kxR+3T0qi8wK/Dt693nM+PEA7KuitX1TAw40jHFxL I1vw== X-Gm-Message-State: ACrzQf0gdHQAcGyQvcet1igJZMI9I7O7fCTjDTJPXeqbGNGbTaizy4jn qYOVAO2+1IWCeeXjbpFNwiYCZrws1y0iYw== X-Google-Smtp-Source: AMsMyM6rNoP+E7/MhZV5ytqeJj5ar8ZG6NLO68FX3UG18CfZOxo1TXeFfiP1U0GjyiQ3zhCEYnrdZw== X-Received: by 2002:a17:906:30c5:b0:782:707:9e2d with SMTP id b5-20020a17090630c500b0078207079e2dmr19774988ejb.286.1666451146078; Sat, 22 Oct 2022 08:05:46 -0700 (PDT) Received: from localhost.localdomain (dynamic-077-191-171-138.77.191.pool.telefonica.de. [77.191.171.138]) by smtp.gmail.com with ESMTPSA id 4-20020a170906310400b00780ab5a9116sm13021558ejx.211.2022.10.22.08.05.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Oct 2022 08:05:45 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aurelien Jarno , Igor Mammedov , Gerd Hoffmann , John Snow , Jiaxun Yang , Ani Sinha , Marcel Apfelbaum , qemu-block@nongnu.org, Richard Henderson , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , "Michael S. Tsirkin" , Paolo Bonzini , Bernhard Beschow Subject: [PATCH v2 00/43] Consolidate PIIX south bridges Date: Sat, 22 Oct 2022 17:04:25 +0200 Message-Id: <20221022150508.26830-1-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=shentey@gmail.com; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This series consolidates the implementations of the PIIX3 and PIIX4 south bridges and is an extended version of [1]. The motivation is to share as much code as possible and to bring both device models to feature parity such that perhaps PIIX4 can become a drop-in-replacement for PIIX3 in the pc machine. This could resolve the "Frankenstein" PIIX4-PM problem in PIIX3 discussed on this list before. The series is structured as follows: First, PIIX3 is changed to instantiate internal devices itself, like PIIX4 does already. Second, PIIX3 gets prepared for the merge with PIIX4 which includes some fixes, cleanups, and renamings. Third, the same is done for PIIX4. In step four the implementations are merged. Since some consolidations could be done easier with merged implementations, the consolidation continues in step five which concludes the series. One particular challenge in this series was that the PIC of PIIX3 used to be instantiated outside of the south bridge while some sub functions require a PIC with populated qemu_irqs. This has been solved by introducing a proxy PIC which furthermore allows PIIX3 to be agnostic towards the virtualization technology used (KVM, TCG, Xen). Due to consolidation PIIX4 gained the PIC as well, possibly allowing the Malta board to gain KVM capabilities in the future. Another challenge was dealing with optional devices where Peter already gave advice in [1] which this series implements. A challenge still remains with consolidating PCI interrupt handling. There are still board-specific piix3_pci_slot_get_pirq() and piix4_pci_slot_get_pirq() which are implemented in isa/piix.c. Any advice how to resolve these would be highly appreaciated. Last but not least there might be some opportunity to consolidate VM state handling, probably by reusing the one from PIIX3. Since I'm not very familiar with the requirements I didn't touch it so far. Testing done: * make check * make check-avocado * Boot live CD: * `qemu-system-x86_64 -M pc -m 2G -accel kvm -cpu host -cdrom manjaro-kde-21.3.2-220704-linux515.iso` * `qemu-system-x86_64 -M q35 -m 2G -accel kvm -cpu host -cdrom manjaro-kde-21.3.2-220704-linux515.iso` * 'qemu-system-mips64el -M malta -kernel vmlinux-3.2.0-4-5kc-malta -hda debian_wheezy_mipsel_standard.qcow2 -append "root=/dev/sda1 console=tty0"` [1] https://lists.nongnu.org/archive/html/qemu-devel/2022-07/msg02348.html v2: - Introduce TYPE_ defines for IDE and USB device models (Mark) - Omit unexporting of PIIXState (Mark) - Improve commit message of patch 5 to mention reset triggering through PCI configuration space (Mark) - Move reviewed patches w/o dependencies to the bottom of the series for early upstreaming -> @Michael? Bernhard Beschow (43): hw/i386/pc: Create DMA controllers in south bridges hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge hw/isa/piix3: Remove extra ';' outside of functions hw/isa/piix3: Add size constraints to rcr_ops hw/isa/piix3: Modernize reset handling hw/isa/piix3: Prefer pci_address_space() over get_system_memory() hw/isa/piix4: Rename wrongly named method hw/ide/piix: Introduce TYPE_ macros for PIIX IDE controllers hw/usb/hcd-uhci: Introduce TYPE_ defines for device models hw/i386/pc: Create RTC controllers in south bridges hw/i386/pc: No need for rtc_state to be an out-parameter hw/isa/piix3: Create USB controller in host device hw/isa/piix3: Create power management controller in host device hw/intc/i8259: Introduce i8259 proxy "isa-pic" hw/isa/piix3: Create ISA PIC in host device hw/isa/piix3: Create IDE controller in host device hw/isa/piix3: Wire up ACPI interrupt internally hw/isa/piix3: Remove unused include hw/isa/piix3: Allow board to provide PCI interrupt routes hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4 hw/isa/piix3: Prefix pci_slot_get_pirq() with "piix3_" hw/isa/piix3: Rename typedef PIIX3State to PIIXState hw/mips/malta: Reuse dev variable meson: Fix dependencies of piix4 southbridge hw/isa/piix4: Add missing initialization hw/isa/piix4: Move pci_ide_create_devs() call to board code hw/isa/piix4: Make PIIX4's ACPI and USB functions optional hw/isa/piix4: Allow board to provide PCI interrupt routes hw/isa/piix4: Remove unused code hw/isa/piix4: Use ISA PIC device hw/isa/piix4: Reuse struct PIIXState from PIIX3 hw/isa/piix4: Rename reset control operations to match PIIX3 hw/isa/piix4: Prefix pci_slot_get_pirq() with "piix4_" hw/isa/piix3: Merge hw/isa/piix4.c hw/isa/piix: Harmonize names of reset control memory regions hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 hw/isa/piix: Rename functions to be shared for interrupt triggering hw/isa/piix: Consolidate IRQ triggering hw/isa/piix: Share PIIX3 base class with PIIX4 hw/isa/piix: Drop the "3" from the PIIX base class hw/i386/acpi-build: Resolve PIIX ISA bridge rather than ACPI controller MAINTAINERS | 6 +- configs/devices/mips-softmmu/common.mak | 3 +- hw/i386/Kconfig | 3 +- hw/i386/acpi-build.c | 4 +- hw/i386/pc.c | 19 +- hw/i386/pc_piix.c | 72 ++--- hw/i386/pc_q35.c | 16 +- hw/ide/piix.c | 5 +- hw/intc/i8259.c | 27 ++ hw/isa/Kconfig | 14 +- hw/isa/lpc_ich9.c | 11 + hw/isa/meson.build | 3 +- hw/isa/{piix3.c => piix.c} | 337 ++++++++++++++++++------ hw/isa/piix4.c | 325 ----------------------- hw/mips/malta.c | 34 ++- hw/usb/hcd-uhci.c | 16 +- hw/usb/hcd-uhci.h | 9 + include/hw/i386/ich9.h | 2 + include/hw/i386/pc.h | 2 +- include/hw/ide/piix.h | 7 + include/hw/intc/i8259.h | 14 + include/hw/southbridge/piix.h | 33 ++- 22 files changed, 473 insertions(+), 489 deletions(-) rename hw/isa/{piix3.c => piix.c} (51%) delete mode 100644 hw/isa/piix4.c create mode 100644 include/hw/ide/piix.h Reviewed-by: Philippe Mathieu-Daudé