| Message ID | 20221108125703.1463577-1-apatel@ventanamicro.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Nested virtualization fixes for QEMU | expand |
Hi Alistair, On Tue, Nov 8, 2022 at 6:27 PM Anup Patel <apatel@ventanamicro.com> wrote: > > This series mainly includes fixes discovered while developing nested > virtualization running on QEMU. > > These patches can also be found in the riscv_nested_fixes_v2 branch at: > https://github.com/avpatel/qemu.git > > Changes since v1: > - Added Alistair's Reviewed-by tags to appropriate patches > - Added detailed comment block in PATCH4 > > Anup Patel (5): > target/riscv: Typo fix in sstc() predicate > target/riscv: Update VS timer whenever htimedelta changes > target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP > target/riscv: No need to re-start QEMU timer when timecmp == > UINT64_MAX > target/riscv: Ensure opcode is saved for all relevant instructions Friendly ping ? Regards, Anup > > target/riscv/cpu_helper.c | 2 -- > target/riscv/csr.c | 18 ++++++++++- > target/riscv/insn_trans/trans_rva.c.inc | 10 ++++-- > target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ > target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ > target/riscv/insn_trans/trans_rvh.c.inc | 3 ++ > target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ > target/riscv/insn_trans/trans_rvzfh.c.inc | 2 ++ > target/riscv/insn_trans/trans_svinval.c.inc | 3 ++ > target/riscv/time_helper.c | 36 ++++++++++++++++++--- > 10 files changed, 70 insertions(+), 10 deletions(-) > > -- > 2.34.1 >
On Tue, Nov 8, 2022 at 10:59 PM Anup Patel <apatel@ventanamicro.com> wrote: > > This series mainly includes fixes discovered while developing nested > virtualization running on QEMU. > > These patches can also be found in the riscv_nested_fixes_v2 branch at: > https://github.com/avpatel/qemu.git > > Changes since v1: > - Added Alistair's Reviewed-by tags to appropriate patches > - Added detailed comment block in PATCH4 > > Anup Patel (5): > target/riscv: Typo fix in sstc() predicate > target/riscv: Update VS timer whenever htimedelta changes > target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP > target/riscv: No need to re-start QEMU timer when timecmp == > UINT64_MAX > target/riscv: Ensure opcode is saved for all relevant instructions Thanks! Applied to riscv-to-apply.next Alistair > > target/riscv/cpu_helper.c | 2 -- > target/riscv/csr.c | 18 ++++++++++- > target/riscv/insn_trans/trans_rva.c.inc | 10 ++++-- > target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ > target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ > target/riscv/insn_trans/trans_rvh.c.inc | 3 ++ > target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ > target/riscv/insn_trans/trans_rvzfh.c.inc | 2 ++ > target/riscv/insn_trans/trans_svinval.c.inc | 3 ++ > target/riscv/time_helper.c | 36 ++++++++++++++++++--- > 10 files changed, 70 insertions(+), 10 deletions(-) > > -- > 2.34.1 > >
This series mainly includes fixes discovered while developing nested virtualization running on QEMU. These patches can also be found in the riscv_nested_fixes_v2 branch at: https://github.com/avpatel/qemu.git Changes since v1: - Added Alistair's Reviewed-by tags to appropriate patches - Added detailed comment block in PATCH4 Anup Patel (5): target/riscv: Typo fix in sstc() predicate target/riscv: Update VS timer whenever htimedelta changes target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX target/riscv: Ensure opcode is saved for all relevant instructions target/riscv/cpu_helper.c | 2 -- target/riscv/csr.c | 18 ++++++++++- target/riscv/insn_trans/trans_rva.c.inc | 10 ++++-- target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ target/riscv/insn_trans/trans_rvh.c.inc | 3 ++ target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ target/riscv/insn_trans/trans_rvzfh.c.inc | 2 ++ target/riscv/insn_trans/trans_svinval.c.inc | 3 ++ target/riscv/time_helper.c | 36 ++++++++++++++++++--- 10 files changed, 70 insertions(+), 10 deletions(-)