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([103.97.165.210]) by smtp.gmail.com with ESMTPSA id w15-20020a0568080d4f00b0035a81480ffcsm2342501oik.38.2022.11.08.04.57.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Nov 2022 04:57:54 -0800 (PST) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Richard Henderson , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Subject: [PATCH v2 0/5] Nested virtualization fixes for QEMU Date: Tue, 8 Nov 2022 18:26:58 +0530 Message-Id: <20221108125703.1463577-1-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::235; envelope-from=apatel@ventanamicro.com; helo=mail-oi1-x235.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This series mainly includes fixes discovered while developing nested virtualization running on QEMU. These patches can also be found in the riscv_nested_fixes_v2 branch at: https://github.com/avpatel/qemu.git Changes since v1: - Added Alistair's Reviewed-by tags to appropriate patches - Added detailed comment block in PATCH4 Anup Patel (5): target/riscv: Typo fix in sstc() predicate target/riscv: Update VS timer whenever htimedelta changes target/riscv: Don't clear mask in riscv_cpu_update_mip() for VSTIP target/riscv: No need to re-start QEMU timer when timecmp == UINT64_MAX target/riscv: Ensure opcode is saved for all relevant instructions target/riscv/cpu_helper.c | 2 -- target/riscv/csr.c | 18 ++++++++++- target/riscv/insn_trans/trans_rva.c.inc | 10 ++++-- target/riscv/insn_trans/trans_rvd.c.inc | 2 ++ target/riscv/insn_trans/trans_rvf.c.inc | 2 ++ target/riscv/insn_trans/trans_rvh.c.inc | 3 ++ target/riscv/insn_trans/trans_rvi.c.inc | 2 ++ target/riscv/insn_trans/trans_rvzfh.c.inc | 2 ++ target/riscv/insn_trans/trans_svinval.c.inc | 3 ++ target/riscv/time_helper.c | 36 ++++++++++++++++++--- 10 files changed, 70 insertions(+), 10 deletions(-)