From patchwork Sun Nov 13 02:32:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Weiwei Li X-Patchwork-Id: 13041419 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 53EEFC4332F for ; Sun, 13 Nov 2022 02:35:52 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ou2q5-00036w-H2; Sat, 12 Nov 2022 21:35:17 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ou2q2-000344-L8; Sat, 12 Nov 2022 21:35:14 -0500 Received: from smtp21.cstnet.cn ([159.226.251.21] helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ou2py-0006I7-W7; Sat, 12 Nov 2022 21:35:14 -0500 Received: from localhost.localdomain (unknown [180.165.240.202]) by APP-01 (Coremail) with SMTP id qwCowABH6GnNV3BjuIN9CQ--.57556S2; Sun, 13 Nov 2022 10:34:57 +0800 (CST) From: Weiwei Li To: palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: wangjunqiang@iscas.ac.cn, lazyparser@gmail.com, Weiwei Li Subject: [PATCH v2 0/8] support subsets of code size reduction extension Date: Sun, 13 Nov 2022 10:32:43 +0800 Message-Id: <20221113023251.11047-1-liweiwei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CM-TRANSID: qwCowABH6GnNV3BjuIN9CQ--.57556S2 X-Coremail-Antispam: 1UD129KBjvJXoW7urWUAF1UZry3ArW5WrWfKrg_yoW8uF4rpr 4rC3yakrZ8tFWxJw4ftF1DJw15Ars5WrW5Awn7twn5Ja13ArW5JrsrKw13K3WxJF18WrnF 93WUCr13uw45JFJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUyv14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26r1j6r1xM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j 6F4UM28EF7xvwVC2z280aVAFwI0_Gr0_Cr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4j6r 4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0 I7IYx2IY67AKxVWUJVWUGwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r 4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCF04k20xvY0x0EwIxG rwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4 vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IY x2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Jr0_Gr1lIxAIcVCF04k26c xKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAF wI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7VUbXdbUUUUUU== X-Originating-IP: [180.165.240.202] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass client-ip=159.226.251.21; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This patchset implements RISC-V Zc* extension v1.0.0.RC5.7 version instructions. Specification: https://github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-zce-upstream-v2 To test Zc* implementation, specify cpu argument with 'x-zca=true,x-zcb=true,x-zcf=true,f=true" and "x-zcd=true,d=true" (or "x-zcmp=true,x-zcmt=true" with c or d=false) to enable Zca/Zcb/Zcf and Zcd(or Zcmp,Zcmt) extension support. This implementation can pass the basic zc tests from https://github.com/yulong-plct/zc-test v2: * add check for relationship between Zca/Zcf/Zcd with C/F/D based on related discussion in review of Zc* spec * separate c.fld{sp}/fsd{sp} with fld{sp}/fsd{sp} before support of zcmp/zcmt Weiwei Li (8): target/riscv: add cfg properties for Zc* extension target/riscv: add support for Zca and Zcf extensions target/riscv: add support for Zcd extension target/riscv: add support for Zcb extension target/riscv: add support for Zcmp extension target/riscv: add support for Zcmt extension target/riscv: expose properties for Zc* extension disas/riscv.c: add disasm support for Zc* disas/riscv.c | 287 +++++++++++++++++++++- target/riscv/cpu.c | 56 +++++ target/riscv/cpu.h | 8 + target/riscv/cpu_bits.h | 7 + target/riscv/csr.c | 35 +++ target/riscv/helper.h | 7 + target/riscv/insn16.decode | 52 +++- target/riscv/insn_trans/trans_rvd.c.inc | 18 ++ target/riscv/insn_trans/trans_rvf.c.inc | 8 +- target/riscv/insn_trans/trans_rvi.c.inc | 4 +- target/riscv/insn_trans/trans_rvzce.c.inc | 265 ++++++++++++++++++++ target/riscv/insn_trans/trans_rvzfh.c.inc | 6 +- target/riscv/machine.c | 19 ++ target/riscv/meson.build | 3 +- target/riscv/translate.c | 23 +- target/riscv/zce_helper.c | 244 ++++++++++++++++++ 16 files changed, 1025 insertions(+), 17 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvzce.c.inc create mode 100644 target/riscv/zce_helper.c