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[77.13.7.153]) by smtp.gmail.com with ESMTPSA id de30-20020a1709069bde00b0073d796a1043sm7135444ejc.123.2022.11.16.10.55.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 10:55:37 -0800 (PST) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Eduardo Habkost , Paolo Bonzini , Huacai Chen , Marcel Apfelbaum , Richard Henderson , Jiaxun Yang , "Michael S. Tsirkin" , =?utf-8?q?Herv=C3=A9_Poussineau?= , =?utf-8?q?Philipp?= =?utf-8?q?e_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Bernhard Beschow Subject: [RFC PATCH 0/3] Decouple INTx-to-LNKx routing from south bridges Date: Wed, 16 Nov 2022 19:54:57 +0100 Message-Id: <20221116185500.84019-1-shentey@gmail.com> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=shentey@gmail.com; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org During my PIIX consolidation work [1] I've noticed that both PIIX models have quite different pci_slot_get_pirq() implementations. These functions seem to map PCI INTx pins to input pins of a programmable interrupt router which is AFAIU board-specific. IOW, board-specific assumptions are baked into the device models which prevent e.g. the whole PIIX4 south bridge to be reusable in the PC machine. In this series, I've moved the pci_slot_get_pirq() implementations into their respective boards. This required a hack, however, thus this RFC. The issue is that pci_slot_get_pirq() can only be assigned using pci_bus_irqs() which also wants a pci_set_irq_fn. That function is in turn device-specific. Futhermore, the issue does not only affect PIIX but also the VIA south bridges as demonstrated in the last patch. Any advice for an upstreamable solution would be highly appreciated. Testing done: * `make check` * `make check-avocado` * `qemu-system-ppc -machine pegasos2 -rtc base=localtime -device ati-vga,guest_hwcursor=true,romfile="" -cdrom morphos-3.17.iso -kernel morphos-3.17/boot.img -serial stdio` * `qemu-system-mips64el -M malta -kernel vmlinux-3.2.0-4-5kc-malta -hda debian_wheezy_mipsel_standard.qcow2 -append "root=/dev/sda1 console=ttyS0"` * `qemu-system-x86_64 -M pc -m 2G -cdrom manjaro-kde-21.3.2-220704-linux515.iso` Thanks, Bernhard [1] https://lists.nongnu.org/archive/html/qemu-devel/2022-10/msg03941.html Bernhard Beschow (3): hw/isa/piix3: Decouple INTx-to-LNKx routing which is board-specific hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specific hw/isa/vt82c686: Implement PIRQ routing hw/i386/pc_piix.c | 17 +++++++++++++++++ hw/isa/piix3.c | 16 +++------------- hw/isa/piix4.c | 28 ++-------------------------- hw/isa/vt82c686.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ hw/mips/malta.c | 29 +++++++++++++++++++++++++++++ 5 files changed, 97 insertions(+), 39 deletions(-)