| Message ID | 20221228062028.29415-1-liweiwei@iscas.ac.cn (mailing list archive) |
|---|---|
| Headers | show |
| Series | support subsets of code size reduction extension | expand |
On Wed, Dec 28, 2022 at 4:23 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > This patchset implements RISC-V Zc* extension v1.0.0.RC5.7 version instructions. > > Specification: > https://github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification > > The port is available here: > https://github.com/plctlab/plct-qemu/tree/plct-zce-upstream-v9 > > To test Zc* implementation, specify cpu argument with 'x-zca=true,x-zcb=true,x-zcf=true,f=true" and "x-zcd=true,d=true" (or "x-zcmp=true,x-zcmt=true" with c or d=false) to enable Zca/Zcb/Zcf and Zcd(or Zcmp,Zcmt) extensions support. > > > This implementation can pass the basic zc tests from https://github.com/yulong-plct/zc-test > > v9: > * rebase on riscv-to-apply.next > > v8: > * improve disas support in Patch 9 > > v7: > * Fix description for Zca > > v6： > * fix base address for jump table in Patch 7 > * rebase on riscv-to-apply.next > > v5: > * fix exception unwind problem for cpu_ld*_code in helper of cm_jalt > > v4: > * improve Zcmp suggested by Richard > * fix stateen related check for Zcmt > > v3: > * update the solution for Zcf to the way of Zcd > * update Zcb to reuse gen_load/store > * use trans function instead of helper for push/pop > > v2: > * add check for relationship between Zca/Zcf/Zcd with C/F/D based on related discussion in review of Zc* spec > * separate c.fld{sp}/fsd{sp} with fld{sp}/fsd{sp} before support of zcmp/zcmt > > Weiwei Li (9): > target/riscv: add cfg properties for Zc* extension > target/riscv: add support for Zca extension > target/riscv: add support for Zcf extension > target/riscv: add support for Zcd extension > target/riscv: add support for Zcb extension > target/riscv: add support for Zcmp extension > target/riscv: add support for Zcmt extension > target/riscv: expose properties for Zc* extension > disas/riscv.c: add disasm support for Zc* Thanks! Applied to riscv-to-apply.next Alistair > > disas/riscv.c | 228 +++++++++++++++- > target/riscv/cpu.c | 56 ++++ > target/riscv/cpu.h | 10 + > target/riscv/cpu_bits.h | 7 + > target/riscv/csr.c | 38 ++- > target/riscv/helper.h | 3 + > target/riscv/insn16.decode | 63 ++++- > target/riscv/insn_trans/trans_rvd.c.inc | 18 ++ > target/riscv/insn_trans/trans_rvf.c.inc | 18 ++ > target/riscv/insn_trans/trans_rvi.c.inc | 4 +- > target/riscv/insn_trans/trans_rvzce.c.inc | 313 ++++++++++++++++++++++ > target/riscv/machine.c | 19 ++ > target/riscv/meson.build | 3 +- > target/riscv/translate.c | 15 +- > target/riscv/zce_helper.c | 55 ++++ > 15 files changed, 834 insertions(+), 16 deletions(-) > create mode 100644 target/riscv/insn_trans/trans_rvzce.c.inc > create mode 100644 target/riscv/zce_helper.c > > -- > 2.25.1 > >
On Wed, Dec 28, 2022 at 4:23 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > This patchset implements RISC-V Zc* extension v1.0.0.RC5.7 version instructions. > > Specification: > https://github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification > > The port is available here: > https://github.com/plctlab/plct-qemu/tree/plct-zce-upstream-v9 > > To test Zc* implementation, specify cpu argument with 'x-zca=true,x-zcb=true,x-zcf=true,f=true" and "x-zcd=true,d=true" (or "x-zcmp=true,x-zcmt=true" with c or d=false) to enable Zca/Zcb/Zcf and Zcd(or Zcmp,Zcmt) extensions support. > > > This implementation can pass the basic zc tests from https://github.com/yulong-plct/zc-test > > v9: > * rebase on riscv-to-apply.next > > v8: > * improve disas support in Patch 9 > > v7: > * Fix description for Zca > > v6： > * fix base address for jump table in Patch 7 > * rebase on riscv-to-apply.next > > v5: > * fix exception unwind problem for cpu_ld*_code in helper of cm_jalt > > v4: > * improve Zcmp suggested by Richard > * fix stateen related check for Zcmt > > v3: > * update the solution for Zcf to the way of Zcd > * update Zcb to reuse gen_load/store > * use trans function instead of helper for push/pop > > v2: > * add check for relationship between Zca/Zcf/Zcd with C/F/D based on related discussion in review of Zc* spec > * separate c.fld{sp}/fsd{sp} with fld{sp}/fsd{sp} before support of zcmp/zcmt > > Weiwei Li (9): > target/riscv: add cfg properties for Zc* extension > target/riscv: add support for Zca extension > target/riscv: add support for Zcf extension > target/riscv: add support for Zcd extension > target/riscv: add support for Zcb extension > target/riscv: add support for Zcmp extension > target/riscv: add support for Zcmt extension > target/riscv: expose properties for Zc* extension > disas/riscv.c: add disasm support for Zc* This series broke a range of boards that use specific CPUs. I have dropped it from my tree. Daniel has sent a series that should fix it though (https://www.mail-archive.com/qemu-devel@nongnu.org/msg930952.html). I have applied his fixes. Can you rebase this series on https://github.com/alistair23/qemu/tree/riscv-to-apply.next, test to ensure the SiFive boards continue to work and then re-send the series? Alistair > > disas/riscv.c | 228 +++++++++++++++- > target/riscv/cpu.c | 56 ++++ > target/riscv/cpu.h | 10 + > target/riscv/cpu_bits.h | 7 + > target/riscv/csr.c | 38 ++- > target/riscv/helper.h | 3 + > target/riscv/insn16.decode | 63 ++++- > target/riscv/insn_trans/trans_rvd.c.inc | 18 ++ > target/riscv/insn_trans/trans_rvf.c.inc | 18 ++ > target/riscv/insn_trans/trans_rvi.c.inc | 4 +- > target/riscv/insn_trans/trans_rvzce.c.inc | 313 ++++++++++++++++++++++ > target/riscv/machine.c | 19 ++ > target/riscv/meson.build | 3 +- > target/riscv/translate.c | 15 +- > target/riscv/zce_helper.c | 55 ++++ > 15 files changed, 834 insertions(+), 16 deletions(-) > create mode 100644 target/riscv/insn_trans/trans_rvzce.c.inc > create mode 100644 target/riscv/zce_helper.c > > -- > 2.25.1 > >
On 2023/1/11 13:00, Alistair Francis wrote: > On Wed, Dec 28, 2022 at 4:23 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: >> This patchset implements RISC-V Zc* extension v1.0.0.RC5.7 version instructions. >> >> Specification: >> https://github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification >> >> The port is available here: >> https://github.com/plctlab/plct-qemu/tree/plct-zce-upstream-v9 >> >> To test Zc* implementation, specify cpu argument with 'x-zca=true,x-zcb=true,x-zcf=true,f=true" and "x-zcd=true,d=true" (or "x-zcmp=true,x-zcmt=true" with c or d=false) to enable Zca/Zcb/Zcf and Zcd(or Zcmp,Zcmt) extensions support. >> >> >> This implementation can pass the basic zc tests from https://github.com/yulong-plct/zc-test >> >> v9: >> * rebase on riscv-to-apply.next >> >> v8: >> * improve disas support in Patch 9 >> >> v7: >> * Fix description for Zca >> >> v6： >> * fix base address for jump table in Patch 7 >> * rebase on riscv-to-apply.next >> >> v5: >> * fix exception unwind problem for cpu_ld*_code in helper of cm_jalt >> >> v4: >> * improve Zcmp suggested by Richard >> * fix stateen related check for Zcmt >> >> v3: >> * update the solution for Zcf to the way of Zcd >> * update Zcb to reuse gen_load/store >> * use trans function instead of helper for push/pop >> >> v2: >> * add check for relationship between Zca/Zcf/Zcd with C/F/D based on related discussion in review of Zc* spec >> * separate c.fld{sp}/fsd{sp} with fld{sp}/fsd{sp} before support of zcmp/zcmt >> >> Weiwei Li (9): >> target/riscv: add cfg properties for Zc* extension >> target/riscv: add support for Zca extension >> target/riscv: add support for Zcf extension >> target/riscv: add support for Zcd extension >> target/riscv: add support for Zcb extension >> target/riscv: add support for Zcmp extension >> target/riscv: add support for Zcmt extension >> target/riscv: expose properties for Zc* extension >> disas/riscv.c: add disasm support for Zc* > This series broke a range of boards that use specific CPUs. I have > dropped it from my tree. > > Daniel has sent a series that should fix it though > (https://www.mail-archive.com/qemu-devel@nongnu.org/msg930952.html). I > have applied his fixes. Can you rebase this series on > https://github.com/alistair23/qemu/tree/riscv-to-apply.next, test to > ensure the SiFive boards continue to work and then re-send the series? > > Alistair This seems "C implies Zca" is not applied on specific CPUs and it'll be fixed if Zc* related check is moved to riscv_cpu_validate_set_extensions just as Daniel's series. I'll rebase on it and test the CPUs in next version. Regards, Weiwei Li >> disas/riscv.c | 228 +++++++++++++++- >> target/riscv/cpu.c | 56 ++++ >> target/riscv/cpu.h | 10 + >> target/riscv/cpu_bits.h | 7 + >> target/riscv/csr.c | 38 ++- >> target/riscv/helper.h | 3 + >> target/riscv/insn16.decode | 63 ++++- >> target/riscv/insn_trans/trans_rvd.c.inc | 18 ++ >> target/riscv/insn_trans/trans_rvf.c.inc | 18 ++ >> target/riscv/insn_trans/trans_rvi.c.inc | 4 +- >> target/riscv/insn_trans/trans_rvzce.c.inc | 313 ++++++++++++++++++++++ >> target/riscv/machine.c | 19 ++ >> target/riscv/meson.build | 3 +- >> target/riscv/translate.c | 15 +- >> target/riscv/zce_helper.c | 55 ++++ >> 15 files changed, 834 insertions(+), 16 deletions(-) >> create mode 100644 target/riscv/insn_trans/trans_rvzce.c.inc >> create mode 100644 target/riscv/zce_helper.c >> >> -- >> 2.25.1 >> >>
This patchset implements RISC-V Zc* extension v1.0.0.RC5.7 version instructions. Specification: https://github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-zce-upstream-v9 To test Zc* implementation, specify cpu argument with 'x-zca=true,x-zcb=true,x-zcf=true,f=true" and "x-zcd=true,d=true" (or "x-zcmp=true,x-zcmt=true" with c or d=false) to enable Zca/Zcb/Zcf and Zcd(or Zcmp,Zcmt) extensions support. This implementation can pass the basic zc tests from https://github.com/yulong-plct/zc-test v9: * rebase on riscv-to-apply.next v8: * improve disas support in Patch 9 v7: * Fix description for Zca v6： * fix base address for jump table in Patch 7 * rebase on riscv-to-apply.next v5: * fix exception unwind problem for cpu_ld*_code in helper of cm_jalt v4: * improve Zcmp suggested by Richard * fix stateen related check for Zcmt v3: * update the solution for Zcf to the way of Zcd * update Zcb to reuse gen_load/store * use trans function instead of helper for push/pop v2: * add check for relationship between Zca/Zcf/Zcd with C/F/D based on related discussion in review of Zc* spec * separate c.fld{sp}/fsd{sp} with fld{sp}/fsd{sp} before support of zcmp/zcmt Weiwei Li (9): target/riscv: add cfg properties for Zc* extension target/riscv: add support for Zca extension target/riscv: add support for Zcf extension target/riscv: add support for Zcd extension target/riscv: add support for Zcb extension target/riscv: add support for Zcmp extension target/riscv: add support for Zcmt extension target/riscv: expose properties for Zc* extension disas/riscv.c: add disasm support for Zc* disas/riscv.c | 228 +++++++++++++++- target/riscv/cpu.c | 56 ++++ target/riscv/cpu.h | 10 + target/riscv/cpu_bits.h | 7 + target/riscv/csr.c | 38 ++- target/riscv/helper.h | 3 + target/riscv/insn16.decode | 63 ++++- target/riscv/insn_trans/trans_rvd.c.inc | 18 ++ target/riscv/insn_trans/trans_rvf.c.inc | 18 ++ target/riscv/insn_trans/trans_rvi.c.inc | 4 +- target/riscv/insn_trans/trans_rvzce.c.inc | 313 ++++++++++++++++++++++ target/riscv/machine.c | 19 ++ target/riscv/meson.build | 3 +- target/riscv/translate.c | 15 +- target/riscv/zce_helper.c | 55 ++++ 15 files changed, 834 insertions(+), 16 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvzce.c.inc create mode 100644 target/riscv/zce_helper.c