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([191.17.222.139]) by smtp.gmail.com with ESMTPSA id bl22-20020a056808309600b0035e7d07bf9dsm6991626oib.16.2022.12.28.05.33.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Dec 2022 05:33:43 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza , Bin Meng Subject: [PATCH v3 00/10] irscv: OpenSBI boot test and cleanups Date: Wed, 28 Dec 2022 10:33:26 -0300 Message-Id: <20221228133336.197467-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.38.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, This new version is still rebased on top of [1]: "[PATCH 00/12] hw/riscv: Improve Spike HTIF emulation fidelity" from Bin Meng. All the changes made were proposed by Phil in the v2 review. * Patches without reviews: 1, 9 Changes from v2: - patch 1: - reduced code repetition with a boot_opensbi() helper - renamed 'opensbi' to 'OpenSBI' in the file header - patch 9: - renamed riscv_load_kernel() to riscv_load_kernel_and_initrd() v2 link: https://mail.gnu.org/archive/html/qemu-devel/2022-12/msg04466.html Changes from v1: - patches were rebased with [1] - patches 13-15: removed * will be re-sent in a follow-up series - patches 4-5: removed since they're picked by Bin in [1] - patch 1: - added a 'skip' riscv32 spike test v1 link: https://mail.gnu.org/archive/html/qemu-devel/2022-12/msg03860.html Based-on: <20221227064812.1903326-1-bmeng@tinylab.org> Cc: Alistair Francis Cc: Bin Meng [1] https://patchwork.ozlabs.org/project/qemu-devel/list/?series=334159 Daniel Henrique Barboza (10): tests/avocado: add RISC-V opensbi boot test hw/riscv/spike: use 'fdt' from MachineState hw/riscv/sifive_u: use 'fdt' from MachineState hw/riscv/spike.c: load initrd right after riscv_load_kernel() hw/riscv: write initrd 'chosen' FDT inside riscv_load_initrd() hw/riscv: write bootargs 'chosen' FDT after riscv_load_kernel() hw/riscv/boot.c: use MachineState in riscv_load_initrd() hw/riscv/boot.c: use MachineState in riscv_load_kernel() hw/riscv/boot.c: introduce riscv_load_kernel_and_initrd() hw/riscv/boot.c: make riscv_load_initrd() static hw/riscv/boot.c | 88 +++++++++++++++++++++------------- hw/riscv/microchip_pfsoc.c | 20 +------- hw/riscv/opentitan.c | 3 +- hw/riscv/sifive_e.c | 4 +- hw/riscv/sifive_u.c | 32 +++---------- hw/riscv/spike.c | 38 ++++----------- hw/riscv/virt.c | 21 +------- include/hw/riscv/boot.h | 8 ++-- include/hw/riscv/sifive_u.h | 3 -- include/hw/riscv/spike.h | 2 - tests/avocado/riscv_opensbi.py | 65 +++++++++++++++++++++++++ 11 files changed, 147 insertions(+), 137 deletions(-) create mode 100644 tests/avocado/riscv_opensbi.py