| Message ID | 20230109172347.1830-1-shentey@gmail.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | Consolidate PIIX south bridges | expand |
Hi Bernhard, On 9/1/23 18:23, Bernhard Beschow wrote: > This series consolidates the implementations of the PIIX3 and PIIX4 south > bridges and is an extended version of [1]. The motivation is to share as much > code as possible and to bring both device models to feature parity such that > perhaps PIIX4 can become a drop-in-replacement for PIIX3 in the pc machine. This > could resolve the "Frankenstein" PIIX4-PM problem in PIIX3 discussed on this > list before. > Bernhard Beschow (30): > hw/pci/pci: Factor out pci_bus_map_irqs() from pci_bus_irqs() > hw/isa/piix3: Decouple INTx-to-LNKx routing which is board-specific > hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specific > hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig > hw/usb/hcd-uhci: Introduce TYPE_ defines for device models > hw/intc/i8259: Make using the isa_pic singleton more type-safe > hw/intc/i8259: Introduce i8259 proxy TYPE_ISA_PIC > hw/i386/pc: Create RTC controllers in south bridges > hw/i386/pc: No need for rtc_state to be an out-parameter > hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 > south bridge > hw/isa/piix3: Create USB controller in host device > hw/isa/piix3: Create power management controller in host device > hw/isa/piix3: Create TYPE_ISA_PIC in host device > hw/isa/piix3: Create IDE controller in host device > hw/isa/piix3: Wire up ACPI interrupt internally > hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS > hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 > hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4 > hw/isa/piix3: Drop the "3" from PIIX base class > hw/isa/piix4: Make PIIX4's ACPI and USB functions optional > hw/isa/piix4: Remove unused inbound ISA interrupt lines > hw/isa/piix4: Use TYPE_ISA_PIC device > hw/isa/piix4: Reuse struct PIIXState from PIIX3 > hw/isa/piix4: Rename reset control operations to match PIIX3 > hw/isa/piix3: Merge hw/isa/piix4.c > hw/isa/piix: Harmonize names of reset control memory regions > hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 > hw/isa/piix: Rename functions to be shared for interrupt triggering > hw/isa/piix: Consolidate IRQ triggering > hw/isa/piix: Share PIIX3's base class with PIIX4 > > Philippe Mathieu-Daudé (3): > hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition > hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader > hw/isa/piix4: Correct IRQRC[A:D] reset values I'm queuing the first 10 patches for now to alleviate the size of this series, and I'll respin a v7 with the rest to avoid making you suffer any longer :/ Thanks for insisting in this effort and I apologize it is taking me so long... Regards, Phil.
Am 13. Januar 2023 08:46:53 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >Hi Bernhard, > >On 9/1/23 18:23, Bernhard Beschow wrote: >> This series consolidates the implementations of the PIIX3 and PIIX4 south >> bridges and is an extended version of [1]. The motivation is to share as much >> code as possible and to bring both device models to feature parity such that >> perhaps PIIX4 can become a drop-in-replacement for PIIX3 in the pc machine. This >> could resolve the "Frankenstein" PIIX4-PM problem in PIIX3 discussed on this >> list before. > >> Bernhard Beschow (30): >> hw/pci/pci: Factor out pci_bus_map_irqs() from pci_bus_irqs() >> hw/isa/piix3: Decouple INTx-to-LNKx routing which is board-specific >> hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specific >> hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig >> hw/usb/hcd-uhci: Introduce TYPE_ defines for device models >> hw/intc/i8259: Make using the isa_pic singleton more type-safe >> hw/intc/i8259: Introduce i8259 proxy TYPE_ISA_PIC >> hw/i386/pc: Create RTC controllers in south bridges >> hw/i386/pc: No need for rtc_state to be an out-parameter >> hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 >> south bridge >> hw/isa/piix3: Create USB controller in host device >> hw/isa/piix3: Create power management controller in host device >> hw/isa/piix3: Create TYPE_ISA_PIC in host device >> hw/isa/piix3: Create IDE controller in host device >> hw/isa/piix3: Wire up ACPI interrupt internally >> hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS >> hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 >> hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4 >> hw/isa/piix3: Drop the "3" from PIIX base class >> hw/isa/piix4: Make PIIX4's ACPI and USB functions optional >> hw/isa/piix4: Remove unused inbound ISA interrupt lines >> hw/isa/piix4: Use TYPE_ISA_PIC device >> hw/isa/piix4: Reuse struct PIIXState from PIIX3 >> hw/isa/piix4: Rename reset control operations to match PIIX3 >> hw/isa/piix3: Merge hw/isa/piix4.c >> hw/isa/piix: Harmonize names of reset control memory regions >> hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 >> hw/isa/piix: Rename functions to be shared for interrupt triggering >> hw/isa/piix: Consolidate IRQ triggering >> hw/isa/piix: Share PIIX3's base class with PIIX4 >> >> Philippe Mathieu-Daudé (3): >> hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition >> hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader >> hw/isa/piix4: Correct IRQRC[A:D] reset values > >I'm queuing the first 10 patches for now to alleviate the size of this >series, and I'll respin a v7 with the rest to avoid making you suffer >any longer :/ Thanks for insisting in this effort and I apologize it >is taking me so long... Okay... What's the further plan? Is there anything missing? Thanks, Bernhard > >Regards, > >Phil.
Am 13. Januar 2023 17:39:45 UTC schrieb Bernhard Beschow <shentey@gmail.com>: > > >Am 13. Januar 2023 08:46:53 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >>Hi Bernhard, >> >>On 9/1/23 18:23, Bernhard Beschow wrote: >>> This series consolidates the implementations of the PIIX3 and PIIX4 south >>> bridges and is an extended version of [1]. The motivation is to share as much >>> code as possible and to bring both device models to feature parity such that >>> perhaps PIIX4 can become a drop-in-replacement for PIIX3 in the pc machine. This >>> could resolve the "Frankenstein" PIIX4-PM problem in PIIX3 discussed on this >>> list before. >> >>> Bernhard Beschow (30): >>> hw/pci/pci: Factor out pci_bus_map_irqs() from pci_bus_irqs() >>> hw/isa/piix3: Decouple INTx-to-LNKx routing which is board-specific >>> hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specific >>> hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig >>> hw/usb/hcd-uhci: Introduce TYPE_ defines for device models >>> hw/intc/i8259: Make using the isa_pic singleton more type-safe >>> hw/intc/i8259: Introduce i8259 proxy TYPE_ISA_PIC >>> hw/i386/pc: Create RTC controllers in south bridges >>> hw/i386/pc: No need for rtc_state to be an out-parameter >>> hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 >>> south bridge >>> hw/isa/piix3: Create USB controller in host device >>> hw/isa/piix3: Create power management controller in host device >>> hw/isa/piix3: Create TYPE_ISA_PIC in host device >>> hw/isa/piix3: Create IDE controller in host device >>> hw/isa/piix3: Wire up ACPI interrupt internally >>> hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS >>> hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 >>> hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4 >>> hw/isa/piix3: Drop the "3" from PIIX base class >>> hw/isa/piix4: Make PIIX4's ACPI and USB functions optional >>> hw/isa/piix4: Remove unused inbound ISA interrupt lines >>> hw/isa/piix4: Use TYPE_ISA_PIC device >>> hw/isa/piix4: Reuse struct PIIXState from PIIX3 >>> hw/isa/piix4: Rename reset control operations to match PIIX3 >>> hw/isa/piix3: Merge hw/isa/piix4.c >>> hw/isa/piix: Harmonize names of reset control memory regions >>> hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 >>> hw/isa/piix: Rename functions to be shared for interrupt triggering >>> hw/isa/piix: Consolidate IRQ triggering >>> hw/isa/piix: Share PIIX3's base class with PIIX4 >>> >>> Philippe Mathieu-Daudé (3): >>> hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition >>> hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader >>> hw/isa/piix4: Correct IRQRC[A:D] reset values >> >>I'm queuing the first 10 patches for now to alleviate the size of this >>series, and I'll respin a v7 with the rest to avoid making you suffer >>any longer :/ Thanks for insisting in this effort and I apologize it >>is taking me so long... > >Okay... What's the further plan? Is there anything missing? Ping > >Thanks, >Bernhard >> >>Regards, >> >>Phil.
On 20/1/23 13:22, Bernhard Beschow wrote: > Am 13. Januar 2023 17:39:45 UTC schrieb Bernhard Beschow <shentey@gmail.com>: >> Am 13. Januar 2023 08:46:53 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >>> On 9/1/23 18:23, Bernhard Beschow wrote: >>>> This series consolidates the implementations of the PIIX3 and PIIX4 south >>>> bridges and is an extended version of [1]. The motivation is to share as much >>>> code as possible and to bring both device models to feature parity such that >>>> perhaps PIIX4 can become a drop-in-replacement for PIIX3 in the pc machine. This >>>> could resolve the "Frankenstein" PIIX4-PM problem in PIIX3 discussed on this >>>> list before. >>> >>>> Bernhard Beschow (30): >>>> hw/pci/pci: Factor out pci_bus_map_irqs() from pci_bus_irqs() >>>> hw/isa/piix3: Decouple INTx-to-LNKx routing which is board-specific >>>> hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specific >>>> hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig >>>> hw/usb/hcd-uhci: Introduce TYPE_ defines for device models >>>> hw/intc/i8259: Make using the isa_pic singleton more type-safe >>>> hw/intc/i8259: Introduce i8259 proxy TYPE_ISA_PIC >>>> hw/i386/pc: Create RTC controllers in south bridges >>>> hw/i386/pc: No need for rtc_state to be an out-parameter >>>> hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 >>>> south bridge >>>> hw/isa/piix3: Create USB controller in host device >>>> hw/isa/piix3: Create power management controller in host device >>>> hw/isa/piix3: Create TYPE_ISA_PIC in host device >>>> hw/isa/piix3: Create IDE controller in host device >>>> hw/isa/piix3: Wire up ACPI interrupt internally >>>> hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS >>>> hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 >>>> hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4 >>>> hw/isa/piix3: Drop the "3" from PIIX base class >>>> hw/isa/piix4: Make PIIX4's ACPI and USB functions optional >>>> hw/isa/piix4: Remove unused inbound ISA interrupt lines >>>> hw/isa/piix4: Use TYPE_ISA_PIC device >>>> hw/isa/piix4: Reuse struct PIIXState from PIIX3 >>>> hw/isa/piix4: Rename reset control operations to match PIIX3 >>>> hw/isa/piix3: Merge hw/isa/piix4.c >>>> hw/isa/piix: Harmonize names of reset control memory regions >>>> hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 >>>> hw/isa/piix: Rename functions to be shared for interrupt triggering >>>> hw/isa/piix: Consolidate IRQ triggering >>>> hw/isa/piix: Share PIIX3's base class with PIIX4 >>>> >>>> Philippe Mathieu-Daudé (3): >>>> hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition >>>> hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader >>>> hw/isa/piix4: Correct IRQRC[A:D] reset values >>> >>> I'm queuing the first 10 patches for now to alleviate the size of this >>> series, and I'll respin a v7 with the rest to avoid making you suffer >>> any longer :/ Thanks for insisting in this effort and I apologize it >>> is taking me so long... >> >> Okay... What's the further plan? Is there anything missing? > > Ping The plan is "I'll respin a v7 with the rest".
Am 23. Januar 2023 09:25:51 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >On 20/1/23 13:22, Bernhard Beschow wrote: >> Am 13. Januar 2023 17:39:45 UTC schrieb Bernhard Beschow <shentey@gmail.com>: >>> Am 13. Januar 2023 08:46:53 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >>>> On 9/1/23 18:23, Bernhard Beschow wrote: >>>>> This series consolidates the implementations of the PIIX3 and PIIX4 south >>>>> bridges and is an extended version of [1]. The motivation is to share as much >>>>> code as possible and to bring both device models to feature parity such that >>>>> perhaps PIIX4 can become a drop-in-replacement for PIIX3 in the pc machine. This >>>>> could resolve the "Frankenstein" PIIX4-PM problem in PIIX3 discussed on this >>>>> list before. >>>> >>>>> Bernhard Beschow (30): >>>>> hw/pci/pci: Factor out pci_bus_map_irqs() from pci_bus_irqs() >>>>> hw/isa/piix3: Decouple INTx-to-LNKx routing which is board-specific >>>>> hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specific >>>>> hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig >>>>> hw/usb/hcd-uhci: Introduce TYPE_ defines for device models >>>>> hw/intc/i8259: Make using the isa_pic singleton more type-safe >>>>> hw/intc/i8259: Introduce i8259 proxy TYPE_ISA_PIC >>>>> hw/i386/pc: Create RTC controllers in south bridges >>>>> hw/i386/pc: No need for rtc_state to be an out-parameter >>>>> hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 >>>>> south bridge >>>>> hw/isa/piix3: Create USB controller in host device >>>>> hw/isa/piix3: Create power management controller in host device >>>>> hw/isa/piix3: Create TYPE_ISA_PIC in host device >>>>> hw/isa/piix3: Create IDE controller in host device >>>>> hw/isa/piix3: Wire up ACPI interrupt internally >>>>> hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS >>>>> hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 >>>>> hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4 >>>>> hw/isa/piix3: Drop the "3" from PIIX base class >>>>> hw/isa/piix4: Make PIIX4's ACPI and USB functions optional >>>>> hw/isa/piix4: Remove unused inbound ISA interrupt lines >>>>> hw/isa/piix4: Use TYPE_ISA_PIC device >>>>> hw/isa/piix4: Reuse struct PIIXState from PIIX3 >>>>> hw/isa/piix4: Rename reset control operations to match PIIX3 >>>>> hw/isa/piix3: Merge hw/isa/piix4.c >>>>> hw/isa/piix: Harmonize names of reset control memory regions >>>>> hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 >>>>> hw/isa/piix: Rename functions to be shared for interrupt triggering >>>>> hw/isa/piix: Consolidate IRQ triggering >>>>> hw/isa/piix: Share PIIX3's base class with PIIX4 >>>>> >>>>> Philippe Mathieu-Daudé (3): >>>>> hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition >>>>> hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader >>>>> hw/isa/piix4: Correct IRQRC[A:D] reset values >>>> >>>> I'm queuing the first 10 patches for now to alleviate the size of this >>>> series, and I'll respin a v7 with the rest to avoid making you suffer >>>> any longer :/ Thanks for insisting in this effort and I apologize it >>>> is taking me so long... >>> >>> Okay... What's the further plan? Is there anything missing? >> >> Ping > >The plan is "I'll respin a v7 with the rest". I understood that part. I wonder what the blocking issue is/was. Best regards, Bernhard
Am 23. Januar 2023 15:51:49 UTC schrieb Bernhard Beschow <shentey@gmail.com>: > > >Am 23. Januar 2023 09:25:51 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >>On 20/1/23 13:22, Bernhard Beschow wrote: >>> Am 13. Januar 2023 17:39:45 UTC schrieb Bernhard Beschow <shentey@gmail.com>: >>>> Am 13. Januar 2023 08:46:53 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >>>>> On 9/1/23 18:23, Bernhard Beschow wrote: >>>>>> This series consolidates the implementations of the PIIX3 and PIIX4 south >>>>>> bridges and is an extended version of [1]. The motivation is to share as much >>>>>> code as possible and to bring both device models to feature parity such that >>>>>> perhaps PIIX4 can become a drop-in-replacement for PIIX3 in the pc machine. This >>>>>> could resolve the "Frankenstein" PIIX4-PM problem in PIIX3 discussed on this >>>>>> list before. >>>>> >>>>>> Bernhard Beschow (30): >>>>>> hw/pci/pci: Factor out pci_bus_map_irqs() from pci_bus_irqs() >>>>>> hw/isa/piix3: Decouple INTx-to-LNKx routing which is board-specific >>>>>> hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specific >>>>>> hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig >>>>>> hw/usb/hcd-uhci: Introduce TYPE_ defines for device models >>>>>> hw/intc/i8259: Make using the isa_pic singleton more type-safe >>>>>> hw/intc/i8259: Introduce i8259 proxy TYPE_ISA_PIC >>>>>> hw/i386/pc: Create RTC controllers in south bridges >>>>>> hw/i386/pc: No need for rtc_state to be an out-parameter >>>>>> hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 >>>>>> south bridge >>>>>> hw/isa/piix3: Create USB controller in host device >>>>>> hw/isa/piix3: Create power management controller in host device >>>>>> hw/isa/piix3: Create TYPE_ISA_PIC in host device >>>>>> hw/isa/piix3: Create IDE controller in host device >>>>>> hw/isa/piix3: Wire up ACPI interrupt internally >>>>>> hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS >>>>>> hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 >>>>>> hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4 >>>>>> hw/isa/piix3: Drop the "3" from PIIX base class >>>>>> hw/isa/piix4: Make PIIX4's ACPI and USB functions optional >>>>>> hw/isa/piix4: Remove unused inbound ISA interrupt lines >>>>>> hw/isa/piix4: Use TYPE_ISA_PIC device >>>>>> hw/isa/piix4: Reuse struct PIIXState from PIIX3 >>>>>> hw/isa/piix4: Rename reset control operations to match PIIX3 >>>>>> hw/isa/piix3: Merge hw/isa/piix4.c >>>>>> hw/isa/piix: Harmonize names of reset control memory regions >>>>>> hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 >>>>>> hw/isa/piix: Rename functions to be shared for interrupt triggering >>>>>> hw/isa/piix: Consolidate IRQ triggering >>>>>> hw/isa/piix: Share PIIX3's base class with PIIX4 >>>>>> >>>>>> Philippe Mathieu-Daudé (3): >>>>>> hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition >>>>>> hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader >>>>>> hw/isa/piix4: Correct IRQRC[A:D] reset values >>>>> >>>>> I'm queuing the first 10 patches for now to alleviate the size of this >>>>> series, and I'll respin a v7 with the rest to avoid making you suffer >>>>> any longer :/ Thanks for insisting in this effort and I apologize it >>>>> is taking me so long... >>>> >>>> Okay... What's the further plan? Is there anything missing? >>> >>> Ping >> >>The plan is "I'll respin a v7 with the rest". > >I understood that part. I wonder what the blocking issue is/was. The first part of this series contains piix3 changes such as the ISA proxy pic and movement of rtc. This seems the riskier part of the series to me which I'd like to get feedback on from the field rather sooner than later. The reason is that I can't currently forsee how fast I could react if these changes were merged during (soft) freeze. Is there a possibility to at least get the piix3 part merged already? Maybe perhaps via the pc tree? Thanks, Bernhard > >Best regards, >Bernhard
On 10/2/23 17:27, Bernhard Beschow wrote: > > > Am 23. Januar 2023 15:51:49 UTC schrieb Bernhard Beschow <shentey@gmail.com>: >> >> >> Am 23. Januar 2023 09:25:51 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >>> On 20/1/23 13:22, Bernhard Beschow wrote: >>>> Am 13. Januar 2023 17:39:45 UTC schrieb Bernhard Beschow <shentey@gmail.com>: >>>>> Am 13. Januar 2023 08:46:53 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >>>>>> On 9/1/23 18:23, Bernhard Beschow wrote: >>>>>>> This series consolidates the implementations of the PIIX3 and PIIX4 south >>>>>>> bridges and is an extended version of [1]. The motivation is to share as much >>>>>>> code as possible and to bring both device models to feature parity such that >>>>>>> perhaps PIIX4 can become a drop-in-replacement for PIIX3 in the pc machine. This >>>>>>> could resolve the "Frankenstein" PIIX4-PM problem in PIIX3 discussed on this >>>>>>> list before. >>>>>> >>>>>>> Bernhard Beschow (30): >>>>>>> hw/pci/pci: Factor out pci_bus_map_irqs() from pci_bus_irqs() >>>>>>> hw/isa/piix3: Decouple INTx-to-LNKx routing which is board-specific >>>>>>> hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specific >>>>>>> hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig >>>>>>> hw/usb/hcd-uhci: Introduce TYPE_ defines for device models >>>>>>> hw/intc/i8259: Make using the isa_pic singleton more type-safe >>>>>>> hw/intc/i8259: Introduce i8259 proxy TYPE_ISA_PIC >>>>>>> hw/i386/pc: Create RTC controllers in south bridges >>>>>>> hw/i386/pc: No need for rtc_state to be an out-parameter >>>>>>> hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 >>>>>>> south bridge >>>>>>> hw/isa/piix3: Create USB controller in host device >>>>>>> hw/isa/piix3: Create power management controller in host device >>>>>>> hw/isa/piix3: Create TYPE_ISA_PIC in host device >>>>>>> hw/isa/piix3: Create IDE controller in host device >>>>>>> hw/isa/piix3: Wire up ACPI interrupt internally >>>>>>> hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS >>>>>>> hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 >>>>>>> hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4 >>>>>>> hw/isa/piix3: Drop the "3" from PIIX base class >>>>>>> hw/isa/piix4: Make PIIX4's ACPI and USB functions optional >>>>>>> hw/isa/piix4: Remove unused inbound ISA interrupt lines >>>>>>> hw/isa/piix4: Use TYPE_ISA_PIC device >>>>>>> hw/isa/piix4: Reuse struct PIIXState from PIIX3 >>>>>>> hw/isa/piix4: Rename reset control operations to match PIIX3 >>>>>>> hw/isa/piix3: Merge hw/isa/piix4.c >>>>>>> hw/isa/piix: Harmonize names of reset control memory regions >>>>>>> hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 >>>>>>> hw/isa/piix: Rename functions to be shared for interrupt triggering >>>>>>> hw/isa/piix: Consolidate IRQ triggering >>>>>>> hw/isa/piix: Share PIIX3's base class with PIIX4 >>>>>>> >>>>>>> Philippe Mathieu-Daudé (3): >>>>>>> hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition >>>>>>> hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader >>>>>>> hw/isa/piix4: Correct IRQRC[A:D] reset values >>>>>> >>>>>> I'm queuing the first 10 patches for now to alleviate the size of this >>>>>> series, and I'll respin a v7 with the rest to avoid making you suffer >>>>>> any longer :/ Thanks for insisting in this effort and I apologize it >>>>>> is taking me so long... >>>>> >>>>> Okay... What's the further plan? Is there anything missing? >>>> >>>> Ping >>> >>> The plan is "I'll respin a v7 with the rest". >> >> I understood that part. I wonder what the blocking issue is/was. > > The first part of this series contains piix3 changes such as the ISA proxy pic and movement of rtc. This seems the riskier part of the series to me which I'd like to get feedback on from the field rather sooner than later. The reason is that I can't currently forsee how fast I could react if these changes were merged during (soft) freeze. What bugs me is the i8259 proxy. I applied your patches locally, and am trying to rework to avoid using it. I amend a 'Co-developed-by' tag to patches modified: https://docs.kernel.org/process/submitting-patches.html#when-to-use-acked-by-cc-and-co-developed-by
Am 10. Februar 2023 17:11:06 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >On 10/2/23 17:27, Bernhard Beschow wrote: >> >> >> Am 23. Januar 2023 15:51:49 UTC schrieb Bernhard Beschow <shentey@gmail.com>: >>> >>> >>> Am 23. Januar 2023 09:25:51 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >>>> On 20/1/23 13:22, Bernhard Beschow wrote: >>>>> Am 13. Januar 2023 17:39:45 UTC schrieb Bernhard Beschow <shentey@gmail.com>: >>>>>> Am 13. Januar 2023 08:46:53 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >>>>>>> On 9/1/23 18:23, Bernhard Beschow wrote: >>>>>>>> This series consolidates the implementations of the PIIX3 and PIIX4 south >>>>>>>> bridges and is an extended version of [1]. The motivation is to share as much >>>>>>>> code as possible and to bring both device models to feature parity such that >>>>>>>> perhaps PIIX4 can become a drop-in-replacement for PIIX3 in the pc machine. This >>>>>>>> could resolve the "Frankenstein" PIIX4-PM problem in PIIX3 discussed on this >>>>>>>> list before. >>>>>>> >>>>>>>> Bernhard Beschow (30): >>>>>>>> hw/pci/pci: Factor out pci_bus_map_irqs() from pci_bus_irqs() >>>>>>>> hw/isa/piix3: Decouple INTx-to-LNKx routing which is board-specific >>>>>>>> hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specific >>>>>>>> hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig >>>>>>>> hw/usb/hcd-uhci: Introduce TYPE_ defines for device models >>>>>>>> hw/intc/i8259: Make using the isa_pic singleton more type-safe >>>>>>>> hw/intc/i8259: Introduce i8259 proxy TYPE_ISA_PIC >>>>>>>> hw/i386/pc: Create RTC controllers in south bridges >>>>>>>> hw/i386/pc: No need for rtc_state to be an out-parameter >>>>>>>> hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 >>>>>>>> south bridge >>>>>>>> hw/isa/piix3: Create USB controller in host device >>>>>>>> hw/isa/piix3: Create power management controller in host device >>>>>>>> hw/isa/piix3: Create TYPE_ISA_PIC in host device >>>>>>>> hw/isa/piix3: Create IDE controller in host device >>>>>>>> hw/isa/piix3: Wire up ACPI interrupt internally >>>>>>>> hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS >>>>>>>> hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 >>>>>>>> hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4 >>>>>>>> hw/isa/piix3: Drop the "3" from PIIX base class >>>>>>>> hw/isa/piix4: Make PIIX4's ACPI and USB functions optional >>>>>>>> hw/isa/piix4: Remove unused inbound ISA interrupt lines >>>>>>>> hw/isa/piix4: Use TYPE_ISA_PIC device >>>>>>>> hw/isa/piix4: Reuse struct PIIXState from PIIX3 >>>>>>>> hw/isa/piix4: Rename reset control operations to match PIIX3 >>>>>>>> hw/isa/piix3: Merge hw/isa/piix4.c >>>>>>>> hw/isa/piix: Harmonize names of reset control memory regions >>>>>>>> hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 >>>>>>>> hw/isa/piix: Rename functions to be shared for interrupt triggering >>>>>>>> hw/isa/piix: Consolidate IRQ triggering >>>>>>>> hw/isa/piix: Share PIIX3's base class with PIIX4 >>>>>>>> >>>>>>>> Philippe Mathieu-Daudé (3): >>>>>>>> hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition >>>>>>>> hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader >>>>>>>> hw/isa/piix4: Correct IRQRC[A:D] reset values >>>>>>> >>>>>>> I'm queuing the first 10 patches for now to alleviate the size of this >>>>>>> series, and I'll respin a v7 with the rest to avoid making you suffer >>>>>>> any longer :/ Thanks for insisting in this effort and I apologize it >>>>>>> is taking me so long... >>>>>> >>>>>> Okay... What's the further plan? Is there anything missing? >>>>> >>>>> Ping >>>> >>>> The plan is "I'll respin a v7 with the rest". >>> >>> I understood that part. I wonder what the blocking issue is/was. >> >> The first part of this series contains piix3 changes such as the ISA proxy pic and movement of rtc. This seems the riskier part of the series to me which I'd like to get feedback on from the field rather sooner than later. The reason is that I can't currently forsee how fast I could react if these changes were merged during (soft) freeze. > >What bugs me is the i8259 proxy. I agree that it smells like a workaround for some problem elsewhere. The patch introducing the proxy to piix3 could be replaced by a patch moving: - isa_bus_irqs() into piix3's realize method and - `piix3->pic = x86ms->gsi;` in front of the realize call of piix3. Would that work for you? I could respin then. A first test run with the pc machine seems promising. The Malta machine would need similar treatment. Best regards, Bernhard >I applied your patches locally, and am >trying to rework to avoid using it. I amend a 'Co-developed-by' tag >to patches modified: >https://docs.kernel.org/process/submitting-patches.html#when-to-use-acked-by-cc-and-co-developed-by >
Am 11. Februar 2023 16:23:10 UTC schrieb Bernhard Beschow <shentey@gmail.com>: > > >Am 10. Februar 2023 17:11:06 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >>On 10/2/23 17:27, Bernhard Beschow wrote: >>> >>> >>> Am 23. Januar 2023 15:51:49 UTC schrieb Bernhard Beschow <shentey@gmail.com>: >>>> >>>> >>>> Am 23. Januar 2023 09:25:51 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >>>>> On 20/1/23 13:22, Bernhard Beschow wrote: >>>>>> Am 13. Januar 2023 17:39:45 UTC schrieb Bernhard Beschow <shentey@gmail.com>: >>>>>>> Am 13. Januar 2023 08:46:53 UTC schrieb "Philippe Mathieu-Daudé" <philmd@linaro.org>: >>>>>>>> On 9/1/23 18:23, Bernhard Beschow wrote: >>>>>>>>> This series consolidates the implementations of the PIIX3 and PIIX4 south >>>>>>>>> bridges and is an extended version of [1]. The motivation is to share as much >>>>>>>>> code as possible and to bring both device models to feature parity such that >>>>>>>>> perhaps PIIX4 can become a drop-in-replacement for PIIX3 in the pc machine. This >>>>>>>>> could resolve the "Frankenstein" PIIX4-PM problem in PIIX3 discussed on this >>>>>>>>> list before. >>>>>>>> >>>>>>>>> Bernhard Beschow (30): >>>>>>>>> hw/pci/pci: Factor out pci_bus_map_irqs() from pci_bus_irqs() >>>>>>>>> hw/isa/piix3: Decouple INTx-to-LNKx routing which is board-specific >>>>>>>>> hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specific >>>>>>>>> hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig >>>>>>>>> hw/usb/hcd-uhci: Introduce TYPE_ defines for device models >>>>>>>>> hw/intc/i8259: Make using the isa_pic singleton more type-safe >>>>>>>>> hw/intc/i8259: Introduce i8259 proxy TYPE_ISA_PIC >>>>>>>>> hw/i386/pc: Create RTC controllers in south bridges >>>>>>>>> hw/i386/pc: No need for rtc_state to be an out-parameter >>>>>>>>> hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 >>>>>>>>> south bridge >>>>>>>>> hw/isa/piix3: Create USB controller in host device >>>>>>>>> hw/isa/piix3: Create power management controller in host device >>>>>>>>> hw/isa/piix3: Create TYPE_ISA_PIC in host device >>>>>>>>> hw/isa/piix3: Create IDE controller in host device >>>>>>>>> hw/isa/piix3: Wire up ACPI interrupt internally >>>>>>>>> hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS >>>>>>>>> hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 >>>>>>>>> hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4 >>>>>>>>> hw/isa/piix3: Drop the "3" from PIIX base class >>>>>>>>> hw/isa/piix4: Make PIIX4's ACPI and USB functions optional >>>>>>>>> hw/isa/piix4: Remove unused inbound ISA interrupt lines >>>>>>>>> hw/isa/piix4: Use TYPE_ISA_PIC device >>>>>>>>> hw/isa/piix4: Reuse struct PIIXState from PIIX3 >>>>>>>>> hw/isa/piix4: Rename reset control operations to match PIIX3 >>>>>>>>> hw/isa/piix3: Merge hw/isa/piix4.c >>>>>>>>> hw/isa/piix: Harmonize names of reset control memory regions >>>>>>>>> hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 >>>>>>>>> hw/isa/piix: Rename functions to be shared for interrupt triggering >>>>>>>>> hw/isa/piix: Consolidate IRQ triggering >>>>>>>>> hw/isa/piix: Share PIIX3's base class with PIIX4 >>>>>>>>> >>>>>>>>> Philippe Mathieu-Daudé (3): >>>>>>>>> hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition >>>>>>>>> hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader >>>>>>>>> hw/isa/piix4: Correct IRQRC[A:D] reset values >>>>>>>> >>>>>>>> I'm queuing the first 10 patches for now to alleviate the size of this >>>>>>>> series, and I'll respin a v7 with the rest to avoid making you suffer >>>>>>>> any longer :/ Thanks for insisting in this effort and I apologize it >>>>>>>> is taking me so long... >>>>>>> >>>>>>> Okay... What's the further plan? Is there anything missing? >>>>>> >>>>>> Ping >>>>> >>>>> The plan is "I'll respin a v7 with the rest". >>>> >>>> I understood that part. I wonder what the blocking issue is/was. >>> >>> The first part of this series contains piix3 changes such as the ISA proxy pic and movement of rtc. This seems the riskier part of the series to me which I'd like to get feedback on from the field rather sooner than later. The reason is that I can't currently forsee how fast I could react if these changes were merged during (soft) freeze. >> >>What bugs me is the i8259 proxy. > >I agree that it smells like a workaround for some problem elsewhere. > >The patch introducing the proxy to piix3 could be replaced by a patch moving: >- isa_bus_irqs() into piix3's realize method and >- `piix3->pic = x86ms->gsi;` in front of the realize call of piix3. > >Would that work for you? I could respin then. > >A first test run with the pc machine seems promising. The Malta machine would need similar treatment. v7 is out which doesn't need a PIC proxy. Best regards, Bernhard > >Best regards, >Bernhard > >>I applied your patches locally, and am >>trying to rework to avoid using it. I amend a 'Co-developed-by' tag >>to patches modified: >>https://docs.kernel.org/process/submitting-patches.html#when-to-use-acked-by-cc-and-co-developed-by >>
This series consolidates the implementations of the PIIX3 and PIIX4 south bridges and is an extended version of [1]. The motivation is to share as much code as possible and to bring both device models to feature parity such that perhaps PIIX4 can become a drop-in-replacement for PIIX3 in the pc machine. This could resolve the "Frankenstein" PIIX4-PM problem in PIIX3 discussed on this list before. The series is structured as follows: These patches are included for compatibility, please ignore: * hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition * hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader * hw/isa/piix4: Correct IRQRC[A:D] reset values 'Decouple INTx-to-LNKx routing from south bridges', see [2]: * hw/pci/pci: Factor out pci_bus_map_irqs() from pci_bus_irqs() * hw/isa/piix3: Decouple INTx-to-LNKx routing which is board-specific * hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specific * hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig * hw/usb/hcd-uhci: Introduce TYPE_ defines for device models Allow for making both PIIX south bridges agnostic about the virtualization technology used by allowing to shift the virtualization policies into board code: * hw/intc/i8259: Make using the isa_pic singleton more type-safe * hw/intc/i8259: Introduce i8259 proxy TYPE_ISA_PIC Move sub devices into the PIIX3 south bridge, like PIIX4 does already: * hw/i386/pc: Create RTC controllers in south bridges * hw/i386/pc: No need for rtc_state to be an out-parameter * hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge * hw/isa/piix3: Create USB controller in host device * hw/isa/piix3: Create power management controller in host device * hw/isa/piix3: Create TYPE_ISA_PIC in host device * hw/isa/piix3: Create IDE controller in host device * hw/isa/piix3: Wire up ACPI interrupt internally Make PIIX3 and PIIX4 south bridges more similar: * hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS * hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 * hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4 * hw/isa/piix3: Drop the "3" from PIIX base class * hw/isa/piix4: Make PIIX4's ACPI and USB functions optional * hw/isa/piix4: Remove unused inbound ISA interrupt lines * hw/isa/piix4: Use TYPE_ISA_PIC device * hw/isa/piix4: Reuse struct PIIXState from PIIX3 * hw/isa/piix4: Rename reset control operations to match PIIX3 This patch achieves the main goal of the series: * hw/isa/piix3: Merge hw/isa/piix4.c Perform some further consolidations which were easier to do after the merge: * hw/isa/piix: Harmonize names of reset control memory regions * hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 * hw/isa/piix: Rename functions to be shared for interrupt triggering * hw/isa/piix: Consolidate IRQ triggering * hw/isa/piix: Share PIIX3's base class with PIIX4 One particular challenge in this series was that the PIC of PIIX3 used to be instantiated outside of the south bridge while some sub functions require a PIC with populated qemu_irqs. This has been solved by introducing a proxy PIC which furthermore allows PIIX3 to be agnostic towards the virtualization technology used (KVM, TCG, Xen). Due to consolidation PIIX4 gained the proxy PIC as well. Another challenge was dealing with optional devices where Peter already gave advice in [1] which this series implements. Last but not least there might be some opportunity to consolidate VM state handling, probably by reusing the one from PIIX3. Since I'm not very familiar with the requirements I didn't touch it so far. v6: - Fix some comments about TYPE_ISA_PIC (Mark) ... and use it consistently within the patch series. - Incorporate series "[PATCH v2 0/3] Decouple INTx-to-LNKx routing from south bridges" [2] for maintainer convenience. - Merge v5's 'hw/i386/pc_piix: Associate pci_map_irq_fn as soon as PCI bus is created' into https://lists.nongnu.org/archive/html/qemu-devel/2022-11/msg03312.html . Do similar for Malta. - Rebase onto latest master (d6271b657286 "Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging") Testing done: * make check * Boot live CD: * `qemu-system-x86_64 -M pc -m 2G -accel kvm -cpu host -cdrom manjaro-kde-21.3.2-220704-linux515.iso` * `qemu-system-x86_64 -M q35 -m 2G -accel kvm -cpu host -cdrom manjaro-kde-21.3.2-220704-linux515.iso` * 'qemu-system-mips64el -M malta -kernel vmlinux-3.2.0-4-5kc-malta -hda debian_wheezy_mipsel_standard.qcow2 -append "root=/dev/sda1 console=ttyS0"` v5: - Pick up Reviewed-by tags from https://lists.nongnu.org/archive/html/qemu-devel/2023-01/msg00116.html - Add patch to make usage of the isa_pic global more type-safe - Re-introduce isa-pic as PIC specific proxy (Mark) v4: - Rebase onto "[PATCH v2 0/3] Decouple INTx-to-LNKx routing from south bridges" since it is already queued via mips-next. This eliminates patches 'hw/isa/piix3: Prefix pci_slot_get_pirq() with "piix3_"' and 'hw/isa/piix4: Prefix pci_slot_get_pirq() with "piix4_"'. - Squash 'hw/isa/piix: Drop the "3" from the PIIX base class' into 'hw/isa/piix3: Rename typedef PIIX3State to PIIXState'. I originally only split these patches since I wasn't sure whether renaming a type was allowed. - Add new patch 'hw/i386/pc_piix: Associate pci_map_irq_fn as soon as PCI bus is created' for forther cleanup of INTx-to-LNKx route decoupling. v3: - Introduce one TYPE_ICH9_USB_UHCI(fn) rather than several TYPE_ICH9_USB_UHCIx (Philippe) - Make proxy PIC generic (Philippe) - Track Malta's PIIX dependencies through KConfig - Rebase onto Philippe's 'hw/isa/piix4: Remove MIPS Malta specific bits' series [3] - Also rebase onto latest master to resolve merge conflicts. This required copying Philippe's series as first three patches - please ignore. v2: - Introduce TYPE_ defines for IDE and USB device models (Mark) - Omit unexporting of PIIXState (Mark) - Improve commit message of patch 5 to mention reset triggering through PCI configuration space (Mark) - Move reviewed patches w/o dependencies to the bottom of the series for early upstreaming [1] https://lists.nongnu.org/archive/html/qemu-devel/2022-07/msg02348.html [2] https://lists.nongnu.org/archive/html/qemu-devel/2022-11/msg03310.html [3] https://lists.nongnu.org/archive/html/qemu-devel/2022-10/msg05367.html Bernhard Beschow (30): hw/pci/pci: Factor out pci_bus_map_irqs() from pci_bus_irqs() hw/isa/piix3: Decouple INTx-to-LNKx routing which is board-specific hw/isa/piix4: Decouple INTx-to-LNKx routing which is board-specific hw/mips/Kconfig: Track Malta's PIIX dependencies via Kconfig hw/usb/hcd-uhci: Introduce TYPE_ defines for device models hw/intc/i8259: Make using the isa_pic singleton more type-safe hw/intc/i8259: Introduce i8259 proxy TYPE_ISA_PIC hw/i386/pc: Create RTC controllers in south bridges hw/i386/pc: No need for rtc_state to be an out-parameter hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge hw/isa/piix3: Create USB controller in host device hw/isa/piix3: Create power management controller in host device hw/isa/piix3: Create TYPE_ISA_PIC in host device hw/isa/piix3: Create IDE controller in host device hw/isa/piix3: Wire up ACPI interrupt internally hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS hw/isa/piix3: Rename pci_piix3_props for sharing with PIIX4 hw/isa/piix3: Rename piix3_reset() for sharing with PIIX4 hw/isa/piix3: Drop the "3" from PIIX base class hw/isa/piix4: Make PIIX4's ACPI and USB functions optional hw/isa/piix4: Remove unused inbound ISA interrupt lines hw/isa/piix4: Use TYPE_ISA_PIC device hw/isa/piix4: Reuse struct PIIXState from PIIX3 hw/isa/piix4: Rename reset control operations to match PIIX3 hw/isa/piix3: Merge hw/isa/piix4.c hw/isa/piix: Harmonize names of reset control memory regions hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 hw/isa/piix: Rename functions to be shared for interrupt triggering hw/isa/piix: Consolidate IRQ triggering hw/isa/piix: Share PIIX3's base class with PIIX4 Philippe Mathieu-Daudé (3): hw/mips/malta: Introduce PIIX4_PCI_DEVFN definition hw/mips/malta: Set PIIX4 IRQ routes in embedded bootloader hw/isa/piix4: Correct IRQRC[A:D] reset values configs/devices/mips-softmmu/common.mak | 2 - hw/usb/hcd-uhci.h | 4 + include/hw/i386/ich9.h | 2 + include/hw/i386/pc.h | 2 +- include/hw/intc/i8259.h | 24 +- include/hw/pci/pci.h | 3 +- include/hw/southbridge/piix.h | 31 ++- include/qemu/typedefs.h | 1 + hw/i386/pc.c | 16 +- hw/i386/pc_piix.c | 87 ++++--- hw/i386/pc_q35.c | 20 +- hw/intc/i8259.c | 38 ++- hw/isa/lpc_ich9.c | 8 + hw/isa/{piix3.c => piix.c} | 289 +++++++++++++++------ hw/isa/piix4.c | 327 ------------------------ hw/mips/malta.c | 65 ++++- hw/pci-host/raven.c | 3 +- hw/pci-host/versatile.c | 3 +- hw/pci/pci.c | 12 +- hw/remote/machine.c | 3 +- hw/usb/hcd-uhci.c | 16 +- MAINTAINERS | 6 +- hw/i386/Kconfig | 4 +- hw/isa/Kconfig | 8 +- hw/isa/meson.build | 3 +- hw/mips/Kconfig | 2 + 26 files changed, 479 insertions(+), 500 deletions(-) rename hw/isa/{piix3.c => piix.c} (57%) delete mode 100644 hw/isa/piix4.c