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([152.250.93.24]) by smtp.gmail.com with ESMTPSA id l21-20020a9d7a95000000b0067c87f23476sm6453978otn.57.2023.01.10.12.14.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Jan 2023 12:14:11 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, richard.henderson@linaro.org, Daniel Henrique Barboza Subject: [PATCH 0/2] target/riscv/cpu: fix sifive_u 32/64bits boot in riscv-to-apply.next Date: Tue, 10 Jan 2023 17:14:03 -0300 Message-Id: <20230110201405.247785-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::243; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x243.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, I found this bug when testing my avocado changes in riscv-to-apply.next. The sifive_u board, both 32 and 64 bits, stopped booting OpenSBI. The guest hangs indefinitely. Git bisect points that this patch broke things: 8c3f35d25e7e98655c609b6c1e9f103b9240f8f8 is the first bad commit commit 8c3f35d25e7e98655c609b6c1e9f103b9240f8f8 Author: Weiwei Li Date: Wed Dec 28 14:20:21 2022 +0800 target/riscv: add support for Zca extension Modify the check for C extension to Zca (C implies Zca) (https://github.com/alistair23/qemu/commit/8c3f35d25e7e98655c609b6c1e9f103b9240f8f8) But this patch per se isn't doing anything wrong. The root of the problem is that this patch makes assumptions based on the previous patch: commit a2b409aa6cadc1ed9715e1ab916ddd3dade0ba85 Author: Weiwei Li Date: Wed Dec 28 14:20:20 2022 +0800 target/riscv: add cfg properties for Zc* extension (https://github.com/alistair23/qemu/commit/a2b409aa6cadc1ed9715e1ab916ddd3dade0ba85) Which added a lot of logic and assumptions that are being skipped by all the SiFive boards because, during riscv_cpu_realize(), we have this code: /* If only MISA_EXT is unset for misa, then set it from properties */ if (env->misa_ext == 0) { uint32_t ext = 0; (...) } In short, we have a lot of code that are being skipped by all SiFive CPUs because these CPUs are setting a non-zero value in set_misa() in their respective cpu_init() functions. It's possible to just hack in and fix the SiFive problem in isolate, but I believe we can do better and allow all riscv_cpu_realize() to be executed for all CPUs, regardless of what they've done during their cpu_init(). Daniel Henrique Barboza (2): target/riscv/cpu: set cpu->cfg in register_cpu_props() target/riscv/cpu.c: do not skip misa logic in riscv_cpu_realize() target/riscv/cpu.c | 525 +++++++++++++++++++++++++-------------------- target/riscv/cpu.h | 4 + 2 files changed, 292 insertions(+), 237 deletions(-)