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([191.17.222.2]) by smtp.gmail.com with ESMTPSA id v25-20020a05683011d900b00683e4084740sm10695872otq.10.2023.01.13.09.18.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Jan 2023 09:18:09 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, Daniel Henrique Barboza Subject: [PATCH v7 0/3] hw/riscv: clear kernel_entry high bits with 32bit CPUs Date: Fri, 13 Jan 2023 14:18:02 -0300 Message-Id: <20230113171805.470252-1-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::342; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x342.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, In this version I followed Bin Meng's suggestion and reverted patch 1 back from what it was in the v5, acks included, and added a new patch (3) to fix the problem detected with the Xvisor use case. I believe this reflects that there is nothing particularly wrong with what we did in the v5 patch and we're going an extra mile to fix what, at first glance, is a bug somewhere else. In patch 3 I also followed Phil's idea and used a translate_fn() callback to do the bit clearing. Changes from v6: - patch 1: - restored to the state it was in v5, acks included - patch 3 (new): - clear the higher bits from the result of load_elf_ram_sym() using a translate_fn() callback for 32 bit CPUs v6 link: https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg02630.html Daniel Henrique Barboza (3): hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel() hw/riscv/boot.c: make riscv_load_initrd() static hw/riscv: clear kernel_entry higher bits in load_elf_ram_sym() hw/riscv/boot.c | 111 ++++++++++++++++++++++++------------- hw/riscv/microchip_pfsoc.c | 12 +--- hw/riscv/opentitan.c | 3 +- hw/riscv/sifive_e.c | 4 +- hw/riscv/sifive_u.c | 12 +--- hw/riscv/spike.c | 13 +---- hw/riscv/virt.c | 12 +--- include/hw/riscv/boot.h | 3 +- 8 files changed, 89 insertions(+), 81 deletions(-)