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[173.197.98.118]) by smtp.gmail.com with ESMTPSA id b4-20020a17090a7ac400b0022c35afad5bsm2496763pjl.16.2023.02.01.23.52.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 23:52:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Cc: anders.roxell@linaro.org, qemu-arm@nongnu.org Subject: [PATCH 0/4] target/arm: Cache ARMVAParameters Date: Wed, 1 Feb 2023 21:52:38 -1000 Message-Id: <20230202075242.260793-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Anders, I'm not well versed on tuxrun, and how to make that work with a qemu binary outside of the container, so I'm not sure if I'm comparing apples to bananas. Can you look and see if this fixes the kselftest slowdown you reported? Anyway, for a boot and shutdown of your rootfs, I see: Before: 11.13% [.] aa64_va_parameters 8.38% [.] helper_lookup_tb_ptr 7.37% [.] pauth_computepac 3.79% [.] qht_lookup_custom After: 9.17% [.] helper_lookup_tb_ptr 8.05% [.] pauth_computepac 4.22% [.] qht_lookup_custom 3.68% [.] pauth_addpac ... 1.67% [.] aa64_va_parameters This is all due to the heavy use pauth makes of aa64_va_parameters. It "only" needs 2 parameters, tsz and tbi, but tsz is probably the most expensive part of aa64_va_parameters -- do anything about that and we might as well cache the whole thing. The change from struct+bitfields to uint32_t+FIELD is meant to combat some really ugly code that gcc produced. Seems like they should have compiled to the same thing, more or less, but alas. r~ Richard Henderson (4): target/arm: Flush only required tlbs for TCR_EL[12] target/arm: Store tbi for both insns and data in ARMVAParameters target/arm: Use FIELD for ARMVAParameters target/arm: Cache ARMVAParameters target/arm/cpu.h | 30 +++++++ target/arm/internals.h | 21 +---- target/arm/helper.c | 177 ++++++++++++++++++++++++++++---------- target/arm/pauth_helper.c | 39 +++++---- target/arm/ptw.c | 57 ++++++------ 5 files changed, 217 insertions(+), 107 deletions(-)