[v3,00/10] enable write_misa() and RISCV_FEATURE_* cleanups

Message

Daniel Henrique Barboza Feb. 15, 2023, 6:57 p.m. UTC

Hi,

In this new version the most notable change was in the write_misa()
logic. I decided to follow Bin's suggestion and removed the verification
at the start of the function.

As the result, the patch that removes RISCV_FEATURE_MISA was merged with
the patch that makes this change (patch 2).

I also removed the v2 acks from it since the patch now does something
different than before. Patch 2 is also the only patch that is missing
acks.


Changes from v2:
- all patches but patch 2 are acked/reviewed
- patch 2:
  - remove the RISCV_FEATURE_MISA validation from write_misa()
- v2 link: https://lists.gnu.org/archive/html/qemu-devel/2023-02/msg03934.html


Daniel Henrique Barboza (10):
  target/riscv: do not mask unsupported QEMU extensions in write_misa()
  target/riscv: always allow write_misa() to write MISA
  target/riscv: introduce riscv_cpu_cfg()
  target/riscv: remove RISCV_FEATURE_DEBUG
  target/riscv/cpu.c: error out if EPMP is enabled without PMP
  target/riscv: remove RISCV_FEATURE_EPMP
  target/riscv: remove RISCV_FEATURE_PMP
  hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in
    create_fdt_socket_cpus()
  target/riscv: remove RISCV_FEATURE_MMU
  target/riscv/cpu: remove CPUArchState::features and friends

 hw/riscv/virt.c           |  7 ++++---
 target/riscv/cpu.c        | 19 ++++---------------
 target/riscv/cpu.h        | 28 +++++-----------------------
 target/riscv/cpu_helper.c |  6 +++---
 target/riscv/csr.c        | 18 +++++-------------
 target/riscv/machine.c    | 11 ++++-------
 target/riscv/monitor.c    |  2 +-
 target/riscv/op_helper.c  |  2 +-
 target/riscv/pmp.c        |  8 ++++----
 9 files changed, 31 insertions(+), 70 deletions(-)