| Message ID | 20230307081403.61950-1-liweiwei@iscas.ac.cn (mailing list archive) |
|---|---|
| Headers | show |
| Series | support subsets of code size reduction extension | expand |
Ping! Several updates have been applied to the support of Zc* extensions after v9 was dropped from the riscv-to-apply.next list. Any new comments for them? Regards, Weiwei Li On 2023/3/7 16:13, Weiwei Li wrote: > This patchset implements RISC-V Zc* extension v1.0.3-1 version instructions. > > Specification: > https://github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification > > The port is available here: > https://github.com/plctlab/plct-qemu/tree/plct-zce-upstream-v12 > > To test Zc* implementation, specify cpu argument with 'x-zca=true,x-zcb=true,x-zcf=true,f=true" and "x-zcd=true,d=true" (or "x-zcmp=true,x-zcmt=true" with c or d=false) to enable Zca/Zcb/Zcf and Zcd(or Zcmp,Zcmt) extensions support. We can also specify "x-zce=true,f=true" to enable Zca/Zcb/Zcmp/Zcmt and Zcf. > > This implementation can pass the basic zc tests from https://github.com/yulong-plct/zc-test > > v12 > * add patch 10 to support zce property > * rebase on upstream master: reuse riscv_get_cfg() in patch 7 and remove tcg_temp_free in patch 6 > > v11 > * update format and field name based on the latest spec in patch 5, 6, 7 (without other functional changes) > * rebase on riscv-to-apply.next > > v10: > * rebase on Daniel's series(riscv-to-apply.next) and adjust riscv-tests to test on sifive related CPUs > > v9: > * rebase on riscv-to-apply.next > > v8: > * improve disas support in Patch 9 > > v7: > * Fix description for Zca > > v6： > * fix base address for jump table in Patch 7 > * rebase on riscv-to-apply.next > > v5: > * fix exception unwind problem for cpu_ld*_code in helper of cm_jalt > > v4: > * improve Zcmp suggested by Richard > * fix stateen related check for Zcmt > > v3: > * update the solution for Zcf to the way of Zcd > * update Zcb to reuse gen_load/store > * use trans function instead of helper for push/pop > > v2: > * add check for relationship between Zca/Zcf/Zcd with C/F/D based on related discussion in review of Zc* spec > * separate c.fld{sp}/fsd{sp} with fld{sp}/fsd{sp} before support of zcmp/zcmt > > Weiwei Li (10): > target/riscv: add cfg properties for Zc* extension > target/riscv: add support for Zca extension > target/riscv: add support for Zcf extension > target/riscv: add support for Zcd extension > target/riscv: add support for Zcb extension > target/riscv: add support for Zcmp extension > target/riscv: add support for Zcmt extension > target/riscv: expose properties for Zc* extension > disas/riscv.c: add disasm support for Zc* > target/riscv: Add support for Zce > > disas/riscv.c | 228 +++++++++++++++- > target/riscv/cpu.c | 69 +++++ > target/riscv/cpu.h | 11 + > target/riscv/cpu_bits.h | 7 + > target/riscv/csr.c | 36 ++- > target/riscv/helper.h | 3 + > target/riscv/insn16.decode | 62 ++++- > target/riscv/insn_trans/trans_rvd.c.inc | 18 ++ > target/riscv/insn_trans/trans_rvf.c.inc | 18 ++ > target/riscv/insn_trans/trans_rvi.c.inc | 4 +- > target/riscv/insn_trans/trans_rvzce.c.inc | 311 ++++++++++++++++++++++ > target/riscv/machine.c | 19 ++ > target/riscv/meson.build | 3 +- > target/riscv/translate.c | 15 +- > target/riscv/zce_helper.c | 55 ++++ > 15 files changed, 843 insertions(+), 16 deletions(-) > create mode 100644 target/riscv/insn_trans/trans_rvzce.c.inc > create mode 100644 target/riscv/zce_helper.c >
On Tue, Mar 7, 2023 at 6:16 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote: > > This patchset implements RISC-V Zc* extension v1.0.3-1 version instructions. > > Specification: > https://github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification > > The port is available here: > https://github.com/plctlab/plct-qemu/tree/plct-zce-upstream-v12 > > To test Zc* implementation, specify cpu argument with 'x-zca=true,x-zcb=true,x-zcf=true,f=true" and "x-zcd=true,d=true" (or "x-zcmp=true,x-zcmt=true" with c or d=false) to enable Zca/Zcb/Zcf and Zcd(or Zcmp,Zcmt) extensions support. We can also specify "x-zce=true,f=true" to enable Zca/Zcb/Zcmp/Zcmt and Zcf. > > This implementation can pass the basic zc tests from https://github.com/yulong-plct/zc-test > > v12 > * add patch 10 to support zce property > * rebase on upstream master: reuse riscv_get_cfg() in patch 7 and remove tcg_temp_free in patch 6 > > v11 > * update format and field name based on the latest spec in patch 5, 6, 7 (without other functional changes) > * rebase on riscv-to-apply.next > > v10: > * rebase on Daniel's series(riscv-to-apply.next) and adjust riscv-tests to test on sifive related CPUs > > v9: > * rebase on riscv-to-apply.next > > v8: > * improve disas support in Patch 9 > > v7: > * Fix description for Zca > > v6： > * fix base address for jump table in Patch 7 > * rebase on riscv-to-apply.next > > v5: > * fix exception unwind problem for cpu_ld*_code in helper of cm_jalt > > v4: > * improve Zcmp suggested by Richard > * fix stateen related check for Zcmt > > v3: > * update the solution for Zcf to the way of Zcd > * update Zcb to reuse gen_load/store > * use trans function instead of helper for push/pop > > v2: > * add check for relationship between Zca/Zcf/Zcd with C/F/D based on related discussion in review of Zc* spec > * separate c.fld{sp}/fsd{sp} with fld{sp}/fsd{sp} before support of zcmp/zcmt > > Weiwei Li (10): > target/riscv: add cfg properties for Zc* extension > target/riscv: add support for Zca extension > target/riscv: add support for Zcf extension > target/riscv: add support for Zcd extension > target/riscv: add support for Zcb extension > target/riscv: add support for Zcmp extension > target/riscv: add support for Zcmt extension > target/riscv: expose properties for Zc* extension > disas/riscv.c: add disasm support for Zc* > target/riscv: Add support for Zce Thanks! Applied to riscv-to-apply.next Alistair > > disas/riscv.c | 228 +++++++++++++++- > target/riscv/cpu.c | 69 +++++ > target/riscv/cpu.h | 11 + > target/riscv/cpu_bits.h | 7 + > target/riscv/csr.c | 36 ++- > target/riscv/helper.h | 3 + > target/riscv/insn16.decode | 62 ++++- > target/riscv/insn_trans/trans_rvd.c.inc | 18 ++ > target/riscv/insn_trans/trans_rvf.c.inc | 18 ++ > target/riscv/insn_trans/trans_rvi.c.inc | 4 +- > target/riscv/insn_trans/trans_rvzce.c.inc | 311 ++++++++++++++++++++++ > target/riscv/machine.c | 19 ++ > target/riscv/meson.build | 3 +- > target/riscv/translate.c | 15 +- > target/riscv/zce_helper.c | 55 ++++ > 15 files changed, 843 insertions(+), 16 deletions(-) > create mode 100644 target/riscv/insn_trans/trans_rvzce.c.inc > create mode 100644 target/riscv/zce_helper.c > > -- > 2.25.1 > >
This patchset implements RISC-V Zc* extension v1.0.3-1 version instructions. Specification: https://github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-zce-upstream-v12 To test Zc* implementation, specify cpu argument with 'x-zca=true,x-zcb=true,x-zcf=true,f=true" and "x-zcd=true,d=true" (or "x-zcmp=true,x-zcmt=true" with c or d=false) to enable Zca/Zcb/Zcf and Zcd(or Zcmp,Zcmt) extensions support. We can also specify "x-zce=true,f=true" to enable Zca/Zcb/Zcmp/Zcmt and Zcf. This implementation can pass the basic zc tests from https://github.com/yulong-plct/zc-test v12 * add patch 10 to support zce property * rebase on upstream master: reuse riscv_get_cfg() in patch 7 and remove tcg_temp_free in patch 6 v11 * update format and field name based on the latest spec in patch 5, 6, 7 (without other functional changes) * rebase on riscv-to-apply.next v10: * rebase on Daniel's series(riscv-to-apply.next) and adjust riscv-tests to test on sifive related CPUs v9: * rebase on riscv-to-apply.next v8: * improve disas support in Patch 9 v7: * Fix description for Zca v6： * fix base address for jump table in Patch 7 * rebase on riscv-to-apply.next v5: * fix exception unwind problem for cpu_ld*_code in helper of cm_jalt v4: * improve Zcmp suggested by Richard * fix stateen related check for Zcmt v3: * update the solution for Zcf to the way of Zcd * update Zcb to reuse gen_load/store * use trans function instead of helper for push/pop v2: * add check for relationship between Zca/Zcf/Zcd with C/F/D based on related discussion in review of Zc* spec * separate c.fld{sp}/fsd{sp} with fld{sp}/fsd{sp} before support of zcmp/zcmt Weiwei Li (10): target/riscv: add cfg properties for Zc* extension target/riscv: add support for Zca extension target/riscv: add support for Zcf extension target/riscv: add support for Zcd extension target/riscv: add support for Zcb extension target/riscv: add support for Zcmp extension target/riscv: add support for Zcmt extension target/riscv: expose properties for Zc* extension disas/riscv.c: add disasm support for Zc* target/riscv: Add support for Zce disas/riscv.c | 228 +++++++++++++++- target/riscv/cpu.c | 69 +++++ target/riscv/cpu.h | 11 + target/riscv/cpu_bits.h | 7 + target/riscv/csr.c | 36 ++- target/riscv/helper.h | 3 + target/riscv/insn16.decode | 62 ++++- target/riscv/insn_trans/trans_rvd.c.inc | 18 ++ target/riscv/insn_trans/trans_rvf.c.inc | 18 ++ target/riscv/insn_trans/trans_rvi.c.inc | 4 +- target/riscv/insn_trans/trans_rvzce.c.inc | 311 ++++++++++++++++++++++ target/riscv/machine.c | 19 ++ target/riscv/meson.build | 3 +- target/riscv/translate.c | 15 +- target/riscv/zce_helper.c | 55 ++++ 15 files changed, 843 insertions(+), 16 deletions(-) create mode 100644 target/riscv/insn_trans/trans_rvzce.c.inc create mode 100644 target/riscv/zce_helper.c