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[v3,0/3] target/riscv: Fix mstatus.MPP related support

Message ID 20230407014743.18779-1-liweiwei@iscas.ac.cn (mailing list archive)
Headers show
Series target/riscv: Fix mstatus.MPP related support | expand

Message

Weiwei Li April 7, 2023, 1:47 a.m. UTC
This patchset tries to fix some problems in current implementation for mstatus.MPP

The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-mpp-fix-v3

v3:
* add patch 2 to remove PRV_H, and use PRV_RESERVED instead in some cases
* improve legalize_mpp and assert error message in patch 3

v2:
* Modify commit message and add comment to specify MPP field becomes a WARL field since priv version 1.11 in patch 2
* rebase on riscv-to-apply.next

Weiwei Li (3):
  target/riscv: Fix the mstatus.MPP value after executing MRET
  target/riscv: Use PRV_RESERVED instead of PRV_H
  target/riscv: Legalize MPP value in write_mstatus

 target/riscv/cpu.h        |  2 +-
 target/riscv/cpu_bits.h   |  2 +-
 target/riscv/cpu_helper.c |  8 ++------
 target/riscv/csr.c        | 32 ++++++++++++++++++++++++++++++++
 target/riscv/gdbstub.c    |  2 +-
 target/riscv/op_helper.c  |  5 +++--
 6 files changed, 40 insertions(+), 11 deletions(-)

Comments

Alistair Francis April 11, 2023, 5:34 a.m. UTC | #1
On Fri, Apr 7, 2023 at 11:49 AM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> This patchset tries to fix some problems in current implementation for mstatus.MPP
>
> The port is available here:
> https://github.com/plctlab/plct-qemu/tree/plct-mpp-fix-v3
>
> v3:
> * add patch 2 to remove PRV_H, and use PRV_RESERVED instead in some cases
> * improve legalize_mpp and assert error message in patch 3
>
> v2:
> * Modify commit message and add comment to specify MPP field becomes a WARL field since priv version 1.11 in patch 2
> * rebase on riscv-to-apply.next
>
> Weiwei Li (3):
>   target/riscv: Fix the mstatus.MPP value after executing MRET
>   target/riscv: Use PRV_RESERVED instead of PRV_H
>   target/riscv: Legalize MPP value in write_mstatus

Thanks!

Applied to riscv-to-apply.next

Alistair

>
>  target/riscv/cpu.h        |  2 +-
>  target/riscv/cpu_bits.h   |  2 +-
>  target/riscv/cpu_helper.c |  8 ++------
>  target/riscv/csr.c        | 32 ++++++++++++++++++++++++++++++++
>  target/riscv/gdbstub.c    |  2 +-
>  target/riscv/op_helper.c  |  5 +++--
>  6 files changed, 40 insertions(+), 11 deletions(-)
>
> --
> 2.25.1
>
>