From patchwork Mon May 8 07:58:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?C=C3=A9dric_Le_Goater?= X-Patchwork-Id: 13234209 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 505CCC7EE24 for ; Mon, 8 May 2023 08:00:57 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pvvmJ-0007zZ-AH; Mon, 08 May 2023 03:59:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pvvmF-0007xa-72; Mon, 08 May 2023 03:59:23 -0400 Received: from gandalf.ozlabs.org ([150.107.74.76]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pvvmD-000151-7O; Mon, 08 May 2023 03:59:22 -0400 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4QFDFm5TJsz4x49; Mon, 8 May 2023 17:59:08 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4QFDFk2V7cz4x44; Mon, 8 May 2023 17:59:06 +1000 (AEST) From: =?utf-8?q?C=C3=A9dric_Le_Goater?= To: qemu-arm@nongnu.org Cc: qemu-devel@nongnu.org, Peter Maydell , Joel Stanley , Andrew Jeffery , =?utf-8?q?C=C3=A9dric_Le_Goater?= Subject: [PATCH 00/12] aspeed: fixes and extensions Date: Mon, 8 May 2023 09:58:47 +0200 Message-Id: <20230508075859.3326566-1-clg@kaod.org> X-Mailer: git-send-email 2.40.0 MIME-Version: 1.0 Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=5sq4=A5=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.25, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hello, This series fixes issues spotted by Coverity and adds a couple of improvements for the machine definition. The first is to offer the capability to define all CS of all SPI controllers without introducing new machine types, using a blockdev on the command line : -blockdev node-name=fmc0,driver=file,filename=./flash.img -device mx66u51235f,addr=0x0,bus=ssi.0,drive=fmc0 instead of using drives which relies on the command line order. Ultimately, we will get rid of drive_get(IF_MTD, ...) but we are not there yet. For this, SSIPeripheral is extended with an "addr" property. A second extension is the introduction of a "uart" machine option to let the user define the default UART device of the machine from the QEMU command line : -M ast2500-evb,uart=uart3 Last, a new "vfp-d32" CPU property is added to ARM CPUs to model FPUs implementing VFPv4 without NEON support and with 16 64-bit FPU registers (and not 32 registers). This is the case for the Cortex A7 of the Aspeed AST2600 SoC. I hope I got it right this time. Thanks, C. Cédric Le Goater (12): aspeed/hace: Initialize g_autofree pointer aspeed: Introduce a boot_rom region at the machine level aspeed: Use the boot_rom region of the fby35 machine hw/ssi: Add an "addr" property to SSIPeripheral hw/ssi: Introduce a ssi_get_cs() helper aspeed/smc: Wire CS lines at reset hw/ssi: Check for duplicate addresses aspeed: Create flash devices only when defaults are enabled m25p80: Introduce an helper to retrieve the BlockBackend of a device aspeed: Get the BlockBackend of FMC0 from the flash device aspeed: Introduce a "uart" machine option target/arm: Allow users to set the number of VFP registers docs/system/arm/aspeed.rst | 10 +++++ include/hw/block/flash.h | 4 ++ include/hw/ssi/ssi.h | 5 +++ target/arm/cpu.h | 2 + hw/arm/aspeed.c | 68 ++++++++++++++++++++++------- hw/arm/aspeed_ast2600.c | 2 + hw/arm/fby35.c | 29 ++++++------ hw/arm/stellaris.c | 4 +- hw/arm/xilinx_zynq.c | 1 + hw/arm/xlnx-versal-virt.c | 1 + hw/arm/xlnx-zcu102.c | 2 + hw/block/m25p80.c | 6 +++ hw/microblaze/petalogix_ml605_mmu.c | 1 + hw/misc/aspeed_hace.c | 2 +- hw/ssi/aspeed_smc.c | 8 ++++ hw/ssi/ssi.c | 42 ++++++++++++++++++ target/arm/cpu.c | 32 ++++++++++++++ 17 files changed, 187 insertions(+), 32 deletions(-)