| Message ID | 20230527141910.1885950-1-richard.henderson@linaro.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | fpu: Add float64_to_int{32,64}_modulo | expand |
On 5/27/23 16:19, Richard Henderson wrote: > Extract some common code from Alpha and Arm, and which will > shortly also be required by the RISC-V Zfa extension. > Added a new test for Alpha; I already had a RISU test for Arm. > > > r~ > > > Richard Henderson (4): > fpu: Add float64_to_int{32,64}_modulo > tests/tcg/alpha: Add test for cvttq > target/alpha: Use float64_to_int64_modulo for CVTTQ > target/arm: Use float64_to_int32_modulo for FJCVTZS > > include/fpu/softfloat.h | 3 ++ > fpu/softfloat.c | 31 ++++++++++++ > target/alpha/fpu_helper.c | 85 +++++++-------------------------- > target/arm/vfp_helper.c | 71 +++++---------------------- > tests/tcg/alpha/test-cvttq.c | 78 ++++++++++++++++++++++++++++++ > fpu/softfloat-parts.c.inc | 78 ++++++++++++++++++++++++++++++ > tests/tcg/alpha/Makefile.target | 2 +- > 7 files changed, 221 insertions(+), 127 deletions(-) > create mode 100644 tests/tcg/alpha/test-cvttq.c > ping. r~
On 6/21/23 11:12, Richard Henderson wrote: > On 5/27/23 16:19, Richard Henderson wrote: >> Extract some common code from Alpha and Arm, and which will >> shortly also be required by the RISC-V Zfa extension. >> Added a new test for Alpha; I already had a RISU test for Arm. >> >> >> r~ >> >> >> Richard Henderson (4): >> fpu: Add float64_to_int{32,64}_modulo >> tests/tcg/alpha: Add test for cvttq >> target/alpha: Use float64_to_int64_modulo for CVTTQ >> target/arm: Use float64_to_int32_modulo for FJCVTZS >> >> include/fpu/softfloat.h | 3 ++ >> fpu/softfloat.c | 31 ++++++++++++ >> target/alpha/fpu_helper.c | 85 +++++++-------------------------- >> target/arm/vfp_helper.c | 71 +++++---------------------- >> tests/tcg/alpha/test-cvttq.c | 78 ++++++++++++++++++++++++++++++ >> fpu/softfloat-parts.c.inc | 78 ++++++++++++++++++++++++++++++ >> tests/tcg/alpha/Makefile.target | 2 +- >> 7 files changed, 221 insertions(+), 127 deletions(-) >> create mode 100644 tests/tcg/alpha/test-cvttq.c >> > ping. ping 2. r~
On Sat, May 27, 2023 at 4:19 PM Richard Henderson <richard.henderson@linaro.org> wrote: > > Extract some common code from Alpha and Arm, and which will > shortly also be required by the RISC-V Zfa extension. > Added a new test for Alpha; I already had a RISU test for Arm. Thank you for providing a generic implementation of this conversion! I've rebased the RISC-V Zfa patch onto this series and could implement the fcvtmod.w.d instruction (with a little bit of flag manipulation after calling float64_to_int32()). Reviewed-by: Christoph Muellner <christoph.muellner@vrull.eu> Tested-by: Christoph Muellner <christoph.muellner@vrull.eu> > > > r~ > > > Richard Henderson (4): > fpu: Add float64_to_int{32,64}_modulo > tests/tcg/alpha: Add test for cvttq > target/alpha: Use float64_to_int64_modulo for CVTTQ > target/arm: Use float64_to_int32_modulo for FJCVTZS > > include/fpu/softfloat.h | 3 ++ > fpu/softfloat.c | 31 ++++++++++++ > target/alpha/fpu_helper.c | 85 +++++++-------------------------- > target/arm/vfp_helper.c | 71 +++++---------------------- > tests/tcg/alpha/test-cvttq.c | 78 ++++++++++++++++++++++++++++++ > fpu/softfloat-parts.c.inc | 78 ++++++++++++++++++++++++++++++ > tests/tcg/alpha/Makefile.target | 2 +- > 7 files changed, 221 insertions(+), 127 deletions(-) > create mode 100644 tests/tcg/alpha/test-cvttq.c > > -- > 2.34.1 >
On 5/27/23 16:19, Richard Henderson wrote: > Extract some common code from Alpha and Arm, and which will > shortly also be required by the RISC-V Zfa extension. > Added a new test for Alpha; I already had a RISU test for Arm. > > > r~ > > > Richard Henderson (4): > fpu: Add float64_to_int{32,64}_modulo > tests/tcg/alpha: Add test for cvttq > target/alpha: Use float64_to_int64_modulo for CVTTQ > target/arm: Use float64_to_int32_modulo for FJCVTZS Queued to tcg-next. r~
Extract some common code from Alpha and Arm, and which will shortly also be required by the RISC-V Zfa extension. Added a new test for Alpha; I already had a RISU test for Arm. r~ Richard Henderson (4): fpu: Add float64_to_int{32,64}_modulo tests/tcg/alpha: Add test for cvttq target/alpha: Use float64_to_int64_modulo for CVTTQ target/arm: Use float64_to_int32_modulo for FJCVTZS include/fpu/softfloat.h | 3 ++ fpu/softfloat.c | 31 ++++++++++++ target/alpha/fpu_helper.c | 85 +++++++-------------------------- target/arm/vfp_helper.c | 71 +++++---------------------- tests/tcg/alpha/test-cvttq.c | 78 ++++++++++++++++++++++++++++++ fpu/softfloat-parts.c.inc | 78 ++++++++++++++++++++++++++++++ tests/tcg/alpha/Makefile.target | 2 +- 7 files changed, 221 insertions(+), 127 deletions(-) create mode 100644 tests/tcg/alpha/test-cvttq.c