[v4,0/4] target/riscv: Add Smrnmi support.

Message

Tommy Wu June 8, 2023, 7:23 a.m. UTC

This patchset added support for Smrnmi Extension in RISC-V.

There are four new CSRs and one new instruction added to allow NMI to be
resumable in RISC-V, which are:

=============================================================
  * mnscratch (0x740)
  * mnepc     (0x741)
  * mncause   (0x742)
  * mnstatus  (0x744)
=============================================================
  * mnret: To return from RNMI interrupt/exception handler.
=============================================================

RNMI also has higher priority than any other interrupts or exceptions
and cannot be disabled by software.

RNMI may be used to route to other devices such as Bus Error Unit or
Watchdog Timer in the future.

The interrupt/exception trap handler addresses of RNMI are
implementation defined.

Changelog:

v4 
* Fix some coding style issues.
( Thank Daniel for the suggestions. )

v3
* Update to the newest version of Smrnmi extension specification.

v2
  * split up the series into more commits for convenience of review.
  * add missing rnmi_irqvec and rnmi_excpvec properties to riscv_harts.

Tommy Wu (4):
  target/riscv: Add Smrnmi cpu extension.
  target/riscv: Add Smrnmi CSRs.
  target/riscv: Handle Smrnmi interrupt and exception.
  target/riscv: Add Smrnmi mnret instruction.

 hw/riscv/riscv_hart.c                         | 21 +++++
 include/hw/riscv/riscv_hart.h                 |  4 +
 target/riscv/cpu.c                            | 18 ++++
 target/riscv/cpu.h                            | 11 +++
 target/riscv/cpu_bits.h                       | 23 ++++++
 target/riscv/cpu_helper.c                     | 81 ++++++++++++++++--
 target/riscv/csr.c                            | 82 +++++++++++++++++++
 target/riscv/helper.h                         |  1 +
 target/riscv/insn32.decode                    |  3 +
 .../riscv/insn_trans/trans_privileged.c.inc   | 12 +++
 target/riscv/op_helper.c                      | 49 +++++++++++
 11 files changed, 300 insertions(+), 5 deletions(-)

Comments

Andrew Jones June 8, 2023, 9:43 a.m. UTC | #1

On Thu, Jun 08, 2023 at 12:23:10AM -0700, Tommy Wu wrote:
> This patchset added support for Smrnmi Extension in RISC-V.
> 
> There are four new CSRs and one new instruction added to allow NMI to be
> resumable in RISC-V, which are:
> 
> =============================================================
>   * mnscratch (0x740)
>   * mnepc     (0x741)
>   * mncause   (0x742)
>   * mnstatus  (0x744)
> =============================================================
>   * mnret: To return from RNMI interrupt/exception handler.
> =============================================================
> 
> RNMI also has higher priority than any other interrupts or exceptions
> and cannot be disabled by software.
> 
> RNMI may be used to route to other devices such as Bus Error Unit or
> Watchdog Timer in the future.
> 
> The interrupt/exception trap handler addresses of RNMI are
> implementation defined.

Is there an M-mode software PoC for this with implemented handlers?

Thanks,
drew

> 
> Changelog:
> 
> v4 
> * Fix some coding style issues.
> ( Thank Daniel for the suggestions. )
> 
> v3
> * Update to the newest version of Smrnmi extension specification.
> 
> v2
>   * split up the series into more commits for convenience of review.
>   * add missing rnmi_irqvec and rnmi_excpvec properties to riscv_harts.
> 
> Tommy Wu (4):
>   target/riscv: Add Smrnmi cpu extension.
>   target/riscv: Add Smrnmi CSRs.
>   target/riscv: Handle Smrnmi interrupt and exception.
>   target/riscv: Add Smrnmi mnret instruction.
> 
>  hw/riscv/riscv_hart.c                         | 21 +++++
>  include/hw/riscv/riscv_hart.h                 |  4 +
>  target/riscv/cpu.c                            | 18 ++++
>  target/riscv/cpu.h                            | 11 +++
>  target/riscv/cpu_bits.h                       | 23 ++++++
>  target/riscv/cpu_helper.c                     | 81 ++++++++++++++++--
>  target/riscv/csr.c                            | 82 +++++++++++++++++++
>  target/riscv/helper.h                         |  1 +
>  target/riscv/insn32.decode                    |  3 +
>  .../riscv/insn_trans/trans_privileged.c.inc   | 12 +++
>  target/riscv/op_helper.c                      | 49 +++++++++++
>  11 files changed, 300 insertions(+), 5 deletions(-)
> 
> -- 
> 2.31.1
> 
>

Tommy Wu Aug. 9, 2024, 5:31 a.m. UTC | #2

On Thu, Jun 8, 2023 at 5:43 PM Andrew Jones <[e-mail]> wrote:
>
> On Thu, Jun 08, 2023 at 12:23:10AM -0700, Tommy Wu wrote:
> > This patchset added support for Smrnmi Extension in RISC-V.
> >
> > There are four new CSRs and one new instruction added to allow NMI to be
> > resumable in RISC-V, which are:
> >
> > =============================================================
> >   * mnscratch (0x740)
> >   * mnepc     (0x741)
> >   * mncause   (0x742)
> >   * mnstatus  (0x744)
> > =============================================================
> >   * mnret: To return from RNMI interrupt/exception handler.
> > =============================================================
> >
> > RNMI also has higher priority than any other interrupts or exceptions
> > and cannot be disabled by software.
> >
> > RNMI may be used to route to other devices such as Bus Error Unit or
> > Watchdog Timer in the future.
> >
> > The interrupt/exception trap handler addresses of RNMI are
> > implementation defined.
>
> Is there an M-mode software PoC for this with implemented handlers?
>
> Thanks,
> drew
>

Sorry for the late reply.
We implement a simple RNMI trap handler in the customized OpenSBI [1], and
use the work from Damien Hedde [2] to inject the RNMI interrupt. We can test
the RNMI functionality with the signal injection in the customized QEMU [3].

I’ll include the test case in the latest upstream email.

[1] https://github.com/TommyWu-fdgkhdkgh/opensbi/commits/dev/twu/master
[2] https://lists.gnu.org/archive/html/qemu-devel/2019-06/msg06232.html
[3] https://github.com/TommyWu-fdgkhdkgh/qemu/tree/dev/twu/master

> >
> > Changelog:
> >
> > v4
> > * Fix some coding style issues.
> > ( Thank Daniel for the suggestions. )
> >
> > v3
> > * Update to the newest version of Smrnmi extension specification.
> >
> > v2
> >   * split up the series into more commits for convenience of review.
> >   * add missing rnmi_irqvec and rnmi_excpvec properties to riscv_harts.
> >
> > Tommy Wu (4):
> >   target/riscv: Add Smrnmi cpu extension.
> >   target/riscv: Add Smrnmi CSRs.
> >   target/riscv: Handle Smrnmi interrupt and exception.
> >   target/riscv: Add Smrnmi mnret instruction.
> >
> >  hw/riscv/riscv_hart.c                         | 21 +++++
> >  include/hw/riscv/riscv_hart.h                 |  4 +
> >  target/riscv/cpu.c                            | 18 ++++
> >  target/riscv/cpu.h                            | 11 +++
> >  target/riscv/cpu_bits.h                       | 23 ++++++
> >  target/riscv/cpu_helper.c                     | 81 ++++++++++++++++--
> >  target/riscv/csr.c                            | 82 +++++++++++++++++++
> >  target/riscv/helper.h                         |  1 +
> >  target/riscv/insn32.decode                    |  3 +
> >  .../riscv/insn_trans/trans_privileged.c.inc   | 12 +++
> >  target/riscv/op_helper.c                      | 49 +++++++++++
> >  11 files changed, 300 insertions(+), 5 deletions(-)
> >
> > --
> > 2.31.1
> >
> >