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[v4,0/3] riscv: Add support for the Zfa extension

Message ID 20230630091303.1676486-1-christoph.muellner@vrull.eu (mailing list archive)
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Series riscv: Add support for the Zfa extension | expand

Message

Christoph Müllner June 30, 2023, 9:13 a.m. UTC 
From: Christoph Müllner <christoph.muellner@vrull.eu>

This patch introduces the RISC-V Zfa extension.

The Zfa specification can be found here:
  https://github.com/riscv/riscv-isa-manual/blob/master/src/zfa.tex
The Zfa specifciation is frozen and is in public review since May 3, 2023:
  https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/SED4ntBkabg

The first patch is mostly equal to v3 (plus resolved rebase issues and
fixed whitespace issues). The second patch changes the implementation
of fcvtmod.w.d to use float64_to_int64_modulo(), which is provided
by a patchset from Richard Henderson:
  https://lists.nongnu.org/archive/html/qemu-devel/2023-05/msg07022.html
The third test contains a test for fcvtmod.w.d, which was used for
development. Since compiling this test requires Zfa support in the
RISC-V toolchain (which is not given), this patch is not meant to
be merged as of now.

Changes in v4:
* Rebase and resolve conflicts
* Fix whitespace issue (thanks Rob)
* Add patch to implemnt fcvtmod.w.d using float64_to_int64_modulo()
* Add (demo) test for fcvtmod.w.d

Changes in v3:
* Add disassembler support
* Enable Zfa by default
* Remove forgotten comments in the decoder
* Fix fli translation code (use movi instead of ld)
* Tested against SPEC CPU2017 fprate
* Use floatN_[min|max] for f[min|max]m.* instructions

Changes in v2:
* Remove calls to mark_fs_dirty() in comparison trans functions
* Rewrite fround(nx) using float*_round_to_int()
* Move fli* to translation unit and fix NaN-boxing of NaN values
* Reimplement FCVTMOD.W.D
* Add use of second register in trans_fmvp_d_x()

Christoph Müllner (3):
  riscv: Add support for the Zfa extension
  target/riscv: Use float64_to_int64_modulo for fcvtmod.w.d
  DO NOT MERGE: tests/tcg/riscv64: Add test for fcvtmod.w.d

 disas/riscv.c                             | 151 ++++++
 target/riscv/cpu.c                        |   8 +
 target/riscv/cpu_cfg.h                    |   1 +
 target/riscv/fpu_helper.c                 | 198 ++++++++
 target/riscv/helper.h                     |  19 +
 target/riscv/insn32.decode                |  26 ++
 target/riscv/insn_trans/trans_rvzfa.c.inc | 529 ++++++++++++++++++++++
 target/riscv/translate.c                  |   1 +
 tests/tcg/riscv64/Makefile.target         |   6 +
 tests/tcg/riscv64/test-fcvtmod.c          | 354 +++++++++++++++
 10 files changed, 1293 insertions(+)
 create mode 100644 target/riscv/insn_trans/trans_rvzfa.c.inc
 create mode 100644 tests/tcg/riscv64/test-fcvtmod.c