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[188.255.126.251]) by smtp.gmail.com with ESMTPSA id cb22-20020a170906a45600b0099d804da2e9sm1342667ejb.225.2023.09.08.11.26.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Sep 2023 11:26:45 -0700 (PDT) From: Alexey Baturo To: Cc: baturo.alexey@gmail.com, richard.henderson@linaro.org, palmer@dabbelt.com, Alistair.Francis@wdc.com, zhiwei_liu@linux.alibaba.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [RFC v1 0/8] RISC-V Pointer Masking update to Zjpm v0.6.1 Date: Fri, 8 Sep 2023 18:26:32 +0000 Message-Id: <20230908182640.1102270-1-baturo.alexey@gmail.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=baturo.alexey@gmail.com; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi all, This series of patches intends to update RISC-V Pointer Masking implementation to the latest Zjpm v0.6.1 version. The Pointer Masking functionality is simplified compared to previous version of spec. The changes have been tested with handwritten assembly tests and LLVM HWASAN test suite. Thanks Alexey Baturo (8): target/riscv: Remove obsolete pointer masking extension code target/riscv: Add new S{sn,mn,m}jpm extensions as part of Zjpm v0.6.1 target/riscv: Add new bits in CSRs for Zjpm 0.6.1 Add enum with maximum ignored bits depending on privilege level for Zjpm v0.6.1 target/riscv: Add pointer masking tb flags target/riscv: Add functions to calculate current N masked bits for pointer masking target/riscv: Update address modify functions to take into account pointer masking target/riscv: enable updates for pointer masking variables and thus enable pointer masking extension target/riscv/cpu.c | 18 +- target/riscv/cpu.h | 35 ++-- target/riscv/cpu_bits.h | 88 +-------- target/riscv/cpu_cfg.h | 3 + target/riscv/cpu_helper.c | 99 ++++++----- target/riscv/csr.c | 336 ++--------------------------------- target/riscv/machine.c | 14 +- target/riscv/pmp.c | 6 + target/riscv/pmp.h | 12 +- target/riscv/translate.c | 50 +++--- target/riscv/vector_helper.c | 9 +- 11 files changed, 152 insertions(+), 518 deletions(-)