From patchwork Sat Oct 7 12:38:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13412295 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E273DE95A61 for ; Sat, 7 Oct 2023 12:39:43 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qp6aB-0002oK-KB; Sat, 07 Oct 2023 08:38:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qp6a9-0002o5-M2 for qemu-devel@nongnu.org; Sat, 07 Oct 2023 08:38:57 -0400 Received: from mail-ej1-x62a.google.com ([2a00:1450:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qp6a7-0002jI-KL for qemu-devel@nongnu.org; Sat, 07 Oct 2023 08:38:57 -0400 Received: by mail-ej1-x62a.google.com with SMTP id a640c23a62f3a-9ada2e6e75fso557907766b.2 for ; Sat, 07 Oct 2023 05:38:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1696682332; x=1697287132; darn=nongnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=vgPqA69aUrv5f9GLE+kVG34XsFP4ndqQaPhYRQwQei8=; b=Ax4YpvZt9Px7H96RkNX4I7f1e3FENeGZ+qrZrxSvZVAs81byctuYSkC7tLuDytZkuS J6Acfb9hg76IgjWYCxZu7GNydp2wmy00RL919bBHox4t3cpcSWqBK5RSxR6SCylzgOeX CfnzZzhYMUfh5UrNqXbQ9PJeSnMkivv2wb3ALCrsQrvfZAH0zG28U921Ri83EulakVoi 63xiRICrhe1GIqhpKwvMkIziyn91zD0KZryjAA8EFKy+PQcRJEKtV5tcVcvFiUc0XbQS cHoZSFeqWppCGxeIYMMNpUCWvVUNeLt8ESLq1+W8XZ16YpOgE98bbWHisC9WiXpujert kHhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696682332; x=1697287132; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=vgPqA69aUrv5f9GLE+kVG34XsFP4ndqQaPhYRQwQei8=; b=VIrsIKloivkwbX15KKqRTH1Wl25EW3jtGtABxIosZgLcbLpFwB3hQRlzBEJvGthGB8 egK26LNC1PcH9npQYPb+nsxOnd2/nbD2pgUyRvghSCreK8ceNVTmW7oBN7YU/0fUMfSo mPJyMrbZwxyHEUBQa0iJ0TdEdMGv28IHwU2yN9UtO640R6aEPqBYJioLVi/kuMpDbsuX cozedV+AUwXTWJVhLoVMUnffpjuWZtMJRLWUJMF24a/AKo8JjdTOOd8ecieJTobP0Vu2 P5/JKpDcPEZW8mGzLb6pHq9aCQHh/8smjjKVxYrh0tynErwPpIKhHwXThr9Alsal2nSZ hQ/A== X-Gm-Message-State: AOJu0YycW/9OFzUHzl4vsn9i7sfSZ6vARx02jiDPtCjQRaeAjUsglBuO Wt1ZQ2UHudpthq/Bodh0ShhzV0kt770= X-Google-Smtp-Source: AGHT+IHxN/f2nHZAjIQSBBFRwhthVw+xLPuZ9DaSj/V92MywMAfvUc1qqjz4FAGxDrgJhI6VR0QB2w== X-Received: by 2002:a17:907:7786:b0:9b7:37de:6011 with SMTP id ky6-20020a170907778600b009b737de6011mr10324179ejc.71.1696682331529; Sat, 07 Oct 2023 05:38:51 -0700 (PDT) Received: from archlinux.. (pd95eda61.dip0.t-ipconnect.de. [217.94.218.97]) by smtp.gmail.com with ESMTPSA id e27-20020a170906045b00b009b655c43710sm4241401eja.24.2023.10.07.05.38.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 07 Oct 2023 05:38:51 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Chuck Zmudzinski , Marcel Apfelbaum , =?utf-8?q?Herv=C3=A9_Poussin?= =?utf-8?q?eau?= , Eduardo Habkost , Aurelien Jarno , "Michael S. Tsirkin" , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= , Paolo Bonzini , Richard Henderson , Bernhard Beschow Subject: [PATCH v8 00/29] Consolidate PIIX south bridges Date: Sat, 7 Oct 2023 14:38:08 +0200 Message-ID: <20231007123843.127151-1-shentey@gmail.com> X-Mailer: git-send-email 2.42.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=shentey@gmail.com; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This series consolidates the implementations of the PIIX3 and PIIX4 south bridges and makes PIIX4 usable in the PC machine via an experimental command line parameter. The motivation is to resolve duplicate code between the device models as well as resolving the "Frankenstein" PIIX4-PM problem in PIIX3 discussed on this list before. The series is structured as follows: Patches 1-8 are preparational patches necessary for moving all sub devices into PIIX3, like was done for PIIX4. In isolation these patches can also be seen as general x86 machine cleanup sub series which has merit in its own right -- and could be applied to master if the remainder of the series takes longer to review. Patches 9-13 move PIIX3 sub devices into one device model like already done for PIIX4. Together with the previous sub series these patches form a bigger sub series which also has merit in its own right, and could be applied independent of the remainder of this series as well. The remainder of this series consolidates the PIIX3 and PIIX4 device models. The culmination point is the last commit which makes PIIX4 usable in the PC machine. One challenge was dealing with optional devices where Peter already gave advice in [1] which this series implements. Although PIIX4 is now usable in the PC machine it still has a different binary layout in its VM state. Testing done: * `make check` * `qemu-system-x86_64 -M pc -m 2G -accel kvm -cdrom manjaro-kde-21.3.2-220704-linux515.iso` * `qemu-system-x86_64 -M pc,x-south-bridge=piix4-isa -m 2G -accel kvm -cdrom manjaro-kde-21.3.2-220704-linux515.iso` * `qemu-system-x86_64 -M q35 -m 2G -accel kvm -cdrom manjaro-kde-21.3.2-220704-linux515.iso` * `qemu-system-mips64el -M malta -cpu 5KEc -m 1G -kernel kernel -initrd initrd -append "root=LABEL=rootfs console=ttyS0" -drive file=image.qcow2` * `qemu-system-mips64el -M malta -bios yamon-02.22.bin` * Run HVM domU guest under Xen with manjaro-kde-21.3.2-220704-linux515.iso image v8: - Wire ISA interrupts before device realization - Optionally allow a PIC and PIT to be instantiated in PIIX3 for compatiblity with PIIX4 - Touch ICH9 LPC as far as required for PIIX consolidation - Make PIIX4 usable in the PC machine via an experimental option - Review and rework history, touching every commit and drop R-b tags when changes became too large v7: - Rebase onto master - Avoid the PIC proxy (Phil) The motivation for the PIC proxy was to allow for wiring up ISA interrupts in the south bridges. ISA interrupt wiring requires the GPIO lines to be populated already but pc_piix assigned the interrupts only after realizing PIIX3. By shifting interrupt assignment before realizing, the ISA interrupts are already populated during PIIX3's realize phase where the ISA interrupts are wired up. - New patches: * hw/isa/piix4: Reuse struct PIIXState from PIIX3 * hw/isa/piix4: Create the "intr" property during init() already - Patches with substantial changes (Reviewed-by dropped): * hw/isa/piix3: Move ISA bus IRQ assignments into host device v6: - Fix some comments about TYPE_ISA_PIC (Mark) ... and use it consistently within the patch series. - Incorporate series "[PATCH v2 0/3] Decouple INTx-to-LNKx routing from south bridges" [2] for maintainer convenience. - Merge v5's 'hw/i386/pc_piix: Associate pci_map_irq_fn as soon as PCI bus is created' into https://lists.nongnu.org/archive/html/qemu-devel/2022-11/msg03312.html . Do similar for Malta. - Rebase onto latest master (d6271b657286 "Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging") v5: - Pick up Reviewed-by tags from https://lists.nongnu.org/archive/html/qemu-devel/2023-01/msg00116.html - Add patch to make usage of the isa_pic global more type-safe - Re-introduce isa-pic as PIC specific proxy (Mark) v4: - Rebase onto "[PATCH v2 0/3] Decouple INTx-to-LNKx routing from south bridges" since it is already queued via mips-next. This eliminates patches 'hw/isa/piix3: Prefix pci_slot_get_pirq() with "piix3_"' and 'hw/isa/piix4: Prefix pci_slot_get_pirq() with "piix4_"'. - Squash 'hw/isa/piix: Drop the "3" from the PIIX base class' into 'hw/isa/piix3: Rename typedef PIIX3State to PIIXState'. I originally only split these patches since I wasn't sure whether renaming a type was allowed. - Add new patch 'hw/i386/pc_piix: Associate pci_map_irq_fn as soon as PCI bus is created' for forther cleanup of INTx-to-LNKx route decoupling. v3: - Introduce one TYPE_ICH9_USB_UHCI(fn) rather than several TYPE_ICH9_USB_UHCIx (Philippe) - Make proxy PIC generic (Philippe) - Track Malta's PIIX dependencies through KConfig - Rebase onto Philippe's 'hw/isa/piix4: Remove MIPS Malta specific bits' series [3] - Also rebase onto latest master to resolve merge conflicts. This required copying Philippe's series as first three patches - please ignore. v2: - Introduce TYPE_ defines for IDE and USB device models (Mark) - Omit unexporting of PIIXState (Mark) - Improve commit message of patch 5 to mention reset triggering through PCI configuration space (Mark) - Move reviewed patches w/o dependencies to the bottom of the series for early upstreaming [1] https://lists.nongnu.org/archive/html/qemu-devel/2022-07/msg02348.html [2] https://lists.nongnu.org/archive/html/qemu-devel/2022-11/msg03310.html [3] https://lists.nongnu.org/archive/html/qemu-devel/2022-10/msg05367.html Bernhard Beschow (29): hw/i386/pc: Merge two if statements into one hw/i386/pc_piix: Allow for setting properties before realizing PIIX3 south bridge hw/i386/pc_piix: Assign PIIX3's ISA interrupts before its realize() hw/isa/piix3: Resolve redundant PIIX_NUM_PIC_IRQS hw/i386/pc_piix: Wire PIIX3's ISA interrupts by new "isa-irqs" property hw/i386/pc_piix: Remove redundant "piix3" variable hw/isa/piix3: Rename "pic" attribute to "isa_irqs_in" hw/i386/pc_q35: Wire ICH9 LPC function's interrupts before its realize() hw/isa/piix3: Wire PIC IRQs to ISA bus in host device hw/i386/pc: Wire RTC ISA IRQs in south bridges hw/isa/piix3: Create IDE controller in host device hw/isa/piix3: Create USB controller in host device hw/isa/piix3: Create power management controller in host device hw/isa/piix3: Drop the "3" from PIIX base class name hw/isa/piix4: Remove unused inbound ISA interrupt lines hw/isa/piix4: Rename "isa" attribute to "isa_irqs_in" hw/isa/piix4: Rename reset control operations to match PIIX3 hw/isa/piix4: Reuse struct PIIXState from PIIX3 hw/isa/piix3: Merge hw/isa/piix4.c hw/isa/piix: Allow for optional PIC creation in PIIX3 hw/isa/piix: Allow for optional PIT creation in PIIX3 hw/isa/piix: Harmonize names of reset control memory regions hw/isa/piix: Share PIIX3's base class with PIIX4 hw/isa/piix: Reuse PIIX3 base class' realize method in PIIX4 hw/isa/piix: Rename functions to be shared for PCI interrupt triggering hw/isa/piix: Reuse PIIX3's PCI interrupt triggering in PIIX4 hw/isa/piix: Resolve duplicate code regarding PCI interrupt wiring hw/isa/piix: Implement multi-process QEMU support also for PIIX4 hw/i386/pc_piix: Make PIIX4 south bridge usable in PC machine MAINTAINERS | 6 +- docs/system/target-i386-desc.rst.inc | 8 + include/hw/i386/pc.h | 2 + include/hw/southbridge/piix.h | 28 ++- hw/i386/pc.c | 13 +- hw/i386/pc_piix.c | 125 ++++++++--- hw/i386/pc_q35.c | 14 +- hw/isa/lpc_ich9.c | 9 +- hw/isa/{piix3.c => piix.c} | 281 ++++++++++++++++++------- hw/isa/piix4.c | 302 --------------------------- hw/mips/malta.c | 5 +- hw/i386/Kconfig | 3 +- hw/isa/Kconfig | 8 +- hw/isa/meson.build | 3 +- hw/mips/Kconfig | 2 +- 15 files changed, 358 insertions(+), 451 deletions(-) rename hw/isa/{piix3.c => piix.c} (52%) delete mode 100644 hw/isa/piix4.c