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[217.169.11.214]) by smtp.gmail.com with ESMTPSA id n16-20020a05600c3b9000b0040684abb623sm19709208wms.24.2023.10.11.07.50.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 07:50:48 -0700 (PDT) From: Rob Bradford To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, atishp@rivosinc.com, palmer@dabbelt.com, alistair.francis@wdc.com, bin.meng@windriver.com, liweiwei@iscas.ac.cn, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, Rob Bradford Subject: [PATCH v2 0/6] Support discontinuous PMU counters Date: Wed, 11 Oct 2023 15:45:48 +0100 Message-ID: <20231011145032.81509-1-rbradford@rivosinc.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=rbradford@rivosinc.com; helo=mail-wm1-x333.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Currently the available PMU counters start at HPM3 and run through to the number specified by the "pmu-num" property. There is no requirement in the specification that the available counters be continously numbered. This series add suppport for specifying a discountinuous range of counters though a "pmu-mask" property. v2: * Use cfg.pmu_mask wherever cfg.pmu_num was used previously * Deprecate pmu_num property (warning, comment & updated documentation) * Override default pmu_mask value iff pmu_num changed from default Rob Bradford (6): target/riscv: Propagate error from PMU setup target/riscv: Don't assume PMU counters are continuous target/riscv: Use existing PMU counter mask in FDT generation qemu/bitops.h: Add MAKE_32BIT_MASK macro target/riscv: Add "pmu-mask" property to replace "pmu-num" docs/about/deprecated: Document RISC-V "pmu-num" deprecation docs/about/deprecated.rst | 10 ++++++++++ hw/riscv/virt.c | 2 +- include/qemu/bitops.h | 3 +++ target/riscv/cpu.c | 13 ++++++++++--- target/riscv/cpu_cfg.h | 3 ++- target/riscv/csr.c | 5 +++-- target/riscv/machine.c | 2 +- target/riscv/pmu.c | 35 +++++++++++++++++------------------ target/riscv/pmu.h | 5 +++-- 9 files changed, 50 insertions(+), 28 deletions(-)