[v2,0/3] pnv nest1 chiplet model

Message

Chalapathi V Oct. 12, 2023, 4:06 p.m. UTC

Hello,

For modularity reasons the P10 processor chip is split into multiple
chiplets individually controlled and managed by the pervasive logic.
The boundaries of these chiplets are defined based on physical design
parameters like clock grids, the nature of the functional units as well
as their pervasive requirements (e.g. clock domains). Examples of chiplet
in the P10 chip are processor cores and caches, memory controllers or IO
interfaces like PCIe. Partitioning the processor chip into these chiplets
allows the pervasive logic to test, initialize, control and manage these
chip partitions individually.

In this series, we create a nest1 chiplet model and implements the chiplet
control scom registers on nest1 chiplet. The chiplet control registers does
the initialization and configuration of a chiplet.

Thank You,
Chalapathi

Chalapathi V (3):
  hw/ppc: Add pnv pervasive common chiplet units
  hw/ppc: Add nest1 chiplet model
  hw/ppc: Nest1 chiplet wiring

 hw/ppc/meson.build                |   2 +
 hw/ppc/pnv.c                      |  11 +++
 hw/ppc/pnv_nest1_chiplet.c        | 153 ++++++++++++++++++++++++++++++
 hw/ppc/pnv_pervasive.c            | 151 +++++++++++++++++++++++++++++
 include/hw/ppc/pnv_chip.h         |   2 +
 include/hw/ppc/pnv_nest_chiplet.h |  39 ++++++++
 include/hw/ppc/pnv_pervasive.h    |  39 ++++++++
 include/hw/ppc/pnv_xscom.h        |   3 +
 8 files changed, 400 insertions(+)
 create mode 100644 hw/ppc/pnv_nest1_chiplet.c
 create mode 100644 hw/ppc/pnv_pervasive.c
 create mode 100644 include/hw/ppc/pnv_nest_chiplet.h
 create mode 100644 include/hw/ppc/pnv_pervasive.h